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"Navigating registers in placement for clock network minimization."

Yongqiang Lu et al. (2005)

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DOI: 10.1145/1065579.1065628

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-07

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  dblp key:
  - conf/dac/LuSHZCHH05
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  - https://dblp.org/rec/conf/dac/LuSHZCHH05
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. DAC 2005: 176-181

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