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"Runtime verification of nonlinear analog circuits using incremental ..."

Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan (2013)

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DOI: 10.7873/DATE.2013.019

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  dblp key:
  - conf/date/AhmadyanKV13
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  persistent URL:
  - https://dblp.org/rec/conf/date/AhmadyanKV13
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. DATE 2013: 21-26

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