"Low power synthesis of dynamic logic circuits using fine-grained clock gating."

Nilanjan Banerjee et al. (2006)

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DOI: 10.1109/DATE.2006.243769

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  - https://dblp.org/rec/conf/date/BanerjeeRMB06
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia:
Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867

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