"Delay Minimization and Technology Mapping of Two-Level Structures and ..."

Jovanka Ciric, Gin Yee, Carl Sechen (2000)

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DOI: 10.1109/DATE.2000.840284

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jovanka Ciric, Gin Yee, Carl Sechen:
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282

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