"Area-Efficient Selective Multi-Threshold CMOS Design Methodology for ..."

Takeshi Kitahara et al. (2005)

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DOI: 10.1109/DATE.2005.68

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/date/KitaharaKMSF05
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. DATE 2005: 646-647

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