"Clock data compensation aware clock tree synthesis in digital circuits ..."

Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay (2017)

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DOI: 10.23919/DATE.2017.7927229

access: closed

type: Conference or Workshop Paper

metadata version: 2017-08-14

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Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay:
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation. DATE 2017: 1504-1509

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