"Hierarchy-aware and area-efficient test infrastructure design for ..."

Anuja Sehgal et al. (2006)

> Home

Details and statistics

DOI: 10.1109/DATE.2006.244140

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/date/SehgalGMC06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/SehgalGMC06
Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.