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"Using Formal Verification Techniques to Reduce Simulation and Test Effort."

Odile Laurent, Pierre Michel, Virginie Wiels (2001)

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DOI: 10.1007/3-540-45251-6_27

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

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  dblp key:
  - conf/fm/LaurentMW01
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Odile Laurent, Pierre Michel, Virginie Wiels:
Using Formal Verification Techniques to Reduce Simulation and Test Effort. FME 2001: 465-477

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