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"A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a ..."

Masafumi Takahashi et al. (1996)

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DOI: 10.1109/HPCA.1996.501196

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/hpca/TakahashiTKS96
Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki:
A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. HPCA 1996: 314-322

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