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ORCIDAPCCAS 2006: Singapore
- IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006. IEEE 2006, ISBN 1-4244-0387-1
- Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee:
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. 1-4 - Vipul Katyal, Randall L. Geiger, Degang Chen:
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs. 5-8 - Xin Zhang, Dunshan Yu, Shimin Sheng:
A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs. 9-12 - Gholamreza Nikandish
, Behnam Sedighi, Mehrdad Sharif Bakhtiar:
INL Prediction Method in Pipeline ADCs. 13-16 - Franz Schlögl, Horst Dietrich, Horst Zimmermann:
Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOS. 17-20 - Xian Ping Fan, Pak Kwong Chan:
Improving Source-Follower Buffer for High-Speed ADC Testing. 21-24 - Wang-Chi Cheng, Cheong-Fat Chan, Suyi Tao, King-Keung Mok:
0.7 V Monolithic CMOS LNA for 802.11 A/B WLAN Application. 25-28 - Amit Gopal M. Purohit, Sanjeev Gupta:
A New Linearity Enhancing Technique for Low Noise Amplifiers. 29-32 - Sang-Sun Yoo, Seok-Oh Yun, Soo-Hwan Shin, Hyung-Joun Yoo:
A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN. 33-36 - Jun-Da Chen, Zhi-Ming Lin:
2.4 GHz High IIP3 and Low-Noise Down-conversion Mixer. 37-40 - Zhi-Qiang Lu, Feng-Chang Lai:
Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs Design. 41-44 - Lini Lee, S. S. Jamuar, Roslina Mohd Sidek, S. Khatun:
An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance. 45-48 - Wu-Sheng Lu:
Digital Filter Design: Global Solutions via Polynomial Optimization. 49-52 - Yongzhi Liu, Zhiping Lin:
Design of Arbitrary FIR Digital Filters with Group Delay Constraint. 53-56 - Tian-Bo Deng:
Symmetry Development for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters. 57-60 - Shing-Chow Chan, Kai Man Tsui, S. H. Zhao:
A Methodology for Automatic Hardware Synthesis of Multiplier-less Digital Filters with Prescribed Output Accuracy. 61-64 - Shing-Chow Chan, Kai Man Tsui, Hon Keung Kwan:
A New Method for Designing Constrained Causal Stable IIR Variable Digital Filters. 65-68 - Chun Zhu Yang, Yong Lian:
New Structures for Single Filter Based Frequency-Response Masking Approach. 69-72 - Katsuya Kondo, Asumi Yamachika, Syoji Kobashi, Yutaka Hata:
3D Shape Acquisition and Arbitrary View Image Generation from Monocular Image Based on Primitive Decomposition. 73-76 - Nongluk Eiamjumrus, Supavadee Aramvith:
Cauchy based Rate-Distortion Optimization Model for H.264 Rate Control. 77-80 - Cong-Van Nguyen, David B. H. Tay, Guang Deng:
A Fast Watermarking System for H.264/AVC Video. 81-84 - Yasuhide Wakabayashi, Akira Taguchi:
A New Efficient Approach for Removal of Impulse Noise for Color Images. 85-88 - Risanuri Hidayat, Kobchai Dejhan, P. Moungnoul, Yoshikazu Miyanaga:
A 0.18µm CMOS Gaussian Monocycle Pulse Circuit Design for UWB. 89-92 - Shingo Yoshizawa, Yoshikazu Miyanaga:
VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System. 93-96 - Terence Chan:
RaceCheck: A Race Logic Audit Program For SoC Designs. 97-100 - YuChen Sun, ChingYao Huang:
A Development and Validation Platform for Communication SOC Design. 101-104 - Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. 105-108 - Kun Yang, Chun Zhang, Zhihua Wang:
Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOC. 109-112 - Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen:
An Adaptive Low-Power Control Scheme for On-Chip Network Applications. 113-118 - Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha:
An Efficient Clocking Scheme for On-Chip Communications. 119-122 - Shaodan Ma, Tung-Sang Ng:
Semi-Blind Time Domain Equalization for MIMO-OFDM Systems. 123-126 - Yonghong Zeng, Abdul Rahim Leyman:
Linear Precoding For MIMO STC-OFDM And Blind Channel Estimation. 127-130 - Zhengang Pan, Jingxiu Liu, Lan Chen, Kenichi Higuchi, Mamoru Sawahashi:
Multi-degree Random Cyclic Delay Diversity in MISO Systems with Frequency-Domain Scheduling. 131-134 - Gan Zheng, Kai-Kit Wong, Tung-Sang Ng:
Throughput Maximization in Multiuser MIMO Downlink with Individual QoS Constraints. 135-138 - Huan Xuan Nguyen, Jinho Choi:
Iterative Symbol-by-symbol Decision Feedback Detection for MIMO-ISI Channels. 139-142 - The-Hanh Pham, Arumugam Nallanathan, Ying-Chang Liang:
An EM-Based Joint Channel Estimation and Data Detection for SIMO Systems. 143-146 - Jamil Y. Khan, D. F. Hall, P. D. Turner:
Development of a Wireless Sensor Network System for Power Constrained Applications. 147-150 - Simon Willis, Cornelis Jan Kikkert:
Design of a Long-Range Wireless Sensor Node. 151-154 - Liang Wei, Li Yinhua, Li Jie:
Hierarchical Decision-making of Multi-sensor System for State Estimation of Machining Process. 155-158 - Wei Jing, Xu Pingping:
An Optimized Scheme of Energy Consumption in Wireless Sensor MAC Protocol. 159-162 - Tao Yin, Haigang Yang, Quan Yuan, Guoping Cui:
Noise Analysis and Simulation of Chopper Amplifier. 167-170 - Guo-Ming Sung, Jyi-Hrong Tzeng, Chen-Shen Liao, Shih-Chieh Shu:
A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control. 171-174 - S. Chuenarom, S. Maitreechit, P. Roengruen, V. Tipsuwarnpron:
Low Power Current-Mode Algorithmic ADC in Half Flash (BCD). 175-178 - Kenji Ohno, Hiroki Matsumoto, Kenji Murao:
A Switched-Voltage High-Accuracy Sample/Hold Circuit. 179-182 - Ka-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins:
A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. 183-186 - Hossein Shamsi, Omid Shoaei:
Continuous Time Delta-Sigma Modulators with Arbitrary DAC Waveforms. 187-190 - Hossein Shamsi, Omid Shoaei:
A New Approach for DAC Non-linearity Compensation in Continuous Time Delta Sigma Modulators. 191-194 - Wang-Chi Cheng, Cheong-Fat Chan, Kong-Pang Pun, Oliver Chiu-sing Choy:
Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. 195-198 - Yu-Chun Huang, Zhi-Ming Lin:
High Power CMOS Power Amplifier for WCDMA. 199-202 - Shuilong Huang, Zhihua Wang, Huainan Ma:
A Fast 1.9 GHz Fractional-N/Integer Frequency Synthesizer with a Self-tuning Algorithm. 203-206 - Ro-Min Weng, Bing-Hung Chen:
A CMOS Digitally Controlled RF Variable Gain Amplifier. 207-209 - Hsin-Ming Wu, Ching-Yuan Yang:
A 3.125-GHz Limiting Amplifier for Optical Receiver System. 210-213 - Ko-Chi Kuo, Feng-Ji Wu:
A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-µm CMOS Technology. 214-217 - Yuan-Pei Lin, Chien-Chang Li, See-May Phoong:
Filterbank Framework for Multicarrier Systems with Improved Subcarrier Separation. 218-221 - Zhongkai Zhang, Tamal Bose, Li Xiao, R. Thamvichai:
Performance Analysis of the Deficient Length EDS Adaptive Algorithm. 222-226 - Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy:
An Alternate Approach for Developing Higher Radix FFT Algorithms. 227-230 - M. Khalid Khan, Muhammad Aurangzeb Khan, Mohammad A. U. Khan, Sungyoung Lee:
Signature Verification using Velocity-based Directional Filter Bank. 231-234 - Weimin Jia, Minli Yao, Jianshe Song:
Multidimensional Parameters Estimation of Array Signal Based on Steering Vector. 235-238 - Sheau-Fang Lei, Hsi-Fu Lee:
Wavelet Packet Transform for Scalable Audio Encoder. 239-242 - Chien-Chung Kuo, Sheau-Fang Lei:
Design of a Low Power Architecture for CABAC Encoder in H.264. 243-246 - Hsin-Ju Feng, Chih-Hung Kuo:
Frame Based Error Concealment in H.264/AVC by Refined Motion Prediction. 247-250 - Ji-Kun Lin, Hung-Ming Wang, Jar-Ferr Yang:
Matched Block Detection and Motion Vector Salvage Methods for Fast H.264/AVC Inter Mode Decision. 251-254 - Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang:
An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. 255-258 - Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu:
Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding. 259-262 - Ping-Yu Chen, Pau-Choo Chung:
Modified MMSE DMC and Edge Reserving Concealment for Improving H.264 Error Resilience. 263-266 - Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity. 267-270 - Leibo Liu, Hongying Meng, Milin Zhang:
An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform. 271-274 - Korrai Deergha Rao, Ch. Gangadhar:
VLSI Realization of Adaptive Equalizers of SIMO FIR Second Order Volterra Channels. 275-278 - Kuan Jen Lin, Chuang Hsiang Huang, Cheng Chia Lo:
Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform. 279-282 - Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang:
Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB). 283-286 - King-Keung Mok, Ka-Hung Tsang, Cheong-Fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun:
Adiabatic Smart Card. 287-290 - Won Cheol Lee, Jun Su Rark, Hyung Min Chang:
Space-Time Decision-Directed Equalizer for SIMO Systems based on Affine Projection Algorithm. 291-294 - Jong Yoon Hwang, Dongkyoon Cho, Kwang Soon Kim, Keum-Chan Whang:
A Turbo-BLAST method with Non-Linear MMSE Detector for MIMO-OFDM systems. 295-297 - Seungwoo Han:
An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction Based on Repeated Utilization of Identical PRSC Sequences in Time Domain. 298-301 - Chungwon Park, Hee Yong Youn, Youngmin Kwon:
Efficient Buffer Management for Retry Mechanism in InfiniBand. 302-304 - Jang Woong Park, Jae Hyun Baek, Myung Hoon Sunwoo:
Enhanced Degree Computationless Modified Euclid's Algorithm. 305-308 - Min Woo Kim, Jun Dong Cho:
A VLSI Design of High Speed Bit-level Viterbi Decoder. 309-312 - Ruya Samli, Sabri Arik:
Global Convergence Analysis of Delayed Bidirectional Associative Memory Neural Networks. 313-316 - A. B. Aljunaid, I. AbuElMaaly, Assim Sagahyroon:
Using ANN To Predict The Best HUB Location. 317-320 - Keerthi Laal Kala, M. B. Srinivas:
A Generic Architecture for Intelligent System Hardware. 321-326 - Harya Wicaksana, Septian Hartono, Foo Say Wei:
Recognition of Musical Instruments. 327-330 - Wenbiao Zhou, Yan Zhang, Zhigang Mao:
Pareto based Multi-objective Mapping IP Cores onto NoC Architectures. 331-334 - Mineo Kaneko:
Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules. 335-338 - Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park:
A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems. 339-342 - Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim:
A 4-bit 1.356 Gsps ADC Using Current Processing Method. 343-346 - Jae-Jin Jung, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim:
A 6-bit 2.704Gsps DAC for DS-CDMA UWB. 347-350 - Kyung-Hoon Lee, Young-Jae Cho, Hee-Cheol Choi, Yong-Hyun Park, Doo-Hwan Sa, Young-Lok Kim, Seung-Hoon Lee:
A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter. 351-354 - Seong-Min Ha, Tae-Kyu Nam, Kwang S. Yoon:
An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN. 355-358 - Tian Tong, Jian Liu, Jan H. Mikkelsen, Torben Larsen:
A 0.18µm CMOS Fully Differential RF Demodulator for FM-UWB Based P-PAN Receivers. 359-362 - Ruey-Lue Wang, Shih-Chih Chen, Hsiang-Chen Kuo, Chien-Hsuan Liu:
A 0.18-µm CMOS UWB Low Noise Amplifier for Full-Band (3.1-10.6GHz) Application. 363-366 - Ruey-Lue Wang, Yan-Kuin Su, Chien-Hsuan Liu:
3~5 GHz Cascoded UWB Power Amplifier. 367-369 - De-Mao Chen, Zhi-Ming Lin:
A Fully Integrated 3 to 5 GHz CMOS Mixer with Active Balun for UWB Receiver. 370-373 - Zhongjun Wang, Lee Guek Yeo, Wenzhen Li, Yanxin Yan, Yujing Ting, Masayuki Tomisawa:
A Novel FFT Processor for OFDM UWB Systems. 374-377 - Wu-Sheng Lu, Ana-Maria Sevcenco:
Design of Optimal Decimation and Interpolation Filters for Low Bit-Rate Image Coding. 378-381 - Zhiming Xu, Zhiping Lin, Anamitra Makur:
Multiple Description Image Coding With Hybrid Redundancy. 382-385 - Chao-Hui Huang, Chin-Teng Lin:
Image Enhancement Algorithm for Hexagonal Cellular Neural Networks. 386-389 - Takao Hinamoto, Yukihiro Shibata, Wu-Sheng Lu:
Minimization of L2-Sensitivity for 2-D Separable-Denominator State-Space Digital Filters Subject to L2-Scaling Constraints. 390-393 - I-Hung Khoo, Hari C. Reddy, P. Karivaratha Rajan:
Design of Delta Operator Based 2-D IIR Filters Using Symmetrical Decomposition. 394-397 - Ching-Lung Su, Wei-Sen Yang, Ya-Li Chen, Yao-Chang Yang, Ching-Wen Chen, Jiun-In Guo, Shau-Yin Tseng:
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. 398-401 - Bin Li, Kai-Kuang Ma:
Unequal-arm Adaptive Rood Pattern Search with Early Terminations For Fast Block-matching Motion Estimation on H.264. 402-405 - Seung-Kyun Oh, HyunWook Park:
Motion Vector Estimation and Adatptive Refinement for the MPEG-4 to H.264/AVC Video Transcoder. 406-409 - Anjali K. Mahajan, Sandhya Kondayya, Xiao Su:
Exploiting Reference Frame History in H.264/AVC Motion Estimation. 410-413 - Gwo-Long Li, Mei-Juan Chen:
Fast Motion Estimation Algorithm by Finite-State Side Match for H.264 Video Coding Standard. 414-417 - Himanshu Thapliyal, A. Prasad Vinod:
Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures. 418-421 - Kavallur Gopi Smitha, Hossam A. H. Fahmy, A. Prasad Vinod:
Redundant Adders Consume Less Energy. 422-425 - Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu:
A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. 426-429 - Wang Pengjun, Yu Junjun, Xu Jian:
Design of Clocked Transmission Gate Adiabatic Logic Circuit Based on the 3ECEAC. 430-433 - Behnam Sedighi, Mehrdad Sharif Bakhtiar:
A New Class AB Current-Mode Circuit for Low-Voltage Applications. 434-437 - Anton Blad, Håkan Johansson, Per Löwenborg:
A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences. 438-441 - Jiangling Guo, Sunanda Mitra, Tanja Karp, Brian Nutter:
A Resolution- and Rate- Scalable Image Subband Coding Scheme with Backward Coding of Wavelet Trees. 442-445 - Ya-Wen Wu, Yuan-Pei Lin, Chien-Chang Li, See-May Phoong:
Design of Time Domain Equalizers Incorporating Radio Frequency Interference Suppression. 446-449 - Ari Viholainen, Tero Ihalainen, Tobias Hidalgo Stitz, Yuan Yang, Markku Renfors:
Flexible Filter Bank Dimensioning for Multicarrier Modulation and Frequency Domain Equalization. 450-453 - Dah-Chung Chang, Da-Long Lee:
Prototype Filter Design for a Cosine-Modulated Filterbank Transmultiplexer. 454-457 - Basant K. Mohanty, Pramod Kumar Meher:
VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. 458-461 - Basant K. Mohanty, Pramod Kumar Meher:
Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. 462-465 - Fitri Arnia, Ikue Iizuka, Hiroyuki Kobayashi, Masaaki Fujiyoshi, Hitoshi Kiya:
DCT Sign Only Correlation and Its Application to Image Registration. 466-469 - Kamalesh Kumar Sharma, Shiv Dutt Joshi:
Image Registration using Fractional Fourier Transform. 470-473 - S. Raghunath, Syed Mahfuzul Aziz:
Design of an Area Efficient High-Speed Color FDWT Processor. 474-477 - Shou-Jung Chang, Wen-Yaw Chung, Chiung-Cheng Chuang:
System Design of Implantable Micro-stimulator for Medical Treatments. 478-481 - Wen-Yaw Chung, Chiung-Cheng Chuang, Ji-Ting Chen:
A Wide-Range and High PSRR CMOS Voltage Reference for Implantable Device. 482-485 - John Taylor, Delia Masanotti, Vipin Seetohul, Shiying Hao:
Some Recent Developments in the Design of Biopotential Amplifiers for ENG Recording Systems. 486-489 - Pak Kwong Chan, Grani Adiwena Hanasusanto, Hendrata B. Tan, Vincent Keng Sian Ong:
A Micropower CMOS Amplifier for Portable Surface EMG Recording. 490-493 - Louis-François Tanguay, Mohamad Sawan:
Low Power SAW-Based Oscillator for an Implantable Multisensor Microsystem. 494-497 - Xiao Liu, Andreas Demosthenous, Nick Donaldson:
A Miniaturized, Power-Efficent Stimulator Output Stage Based on the Bridge Rectifier Circuit. 498-501 - Gin Kooi Lim, Tee Hui Teo:
A Low-Power Low-Voltage Amplifier for Heart Rate Sensor. 502-505 - Harikrishnan Ramiah, Tun Zainal Azni Zulkifli:
Design of 3-4GHz Tunable Low Noise LC-QVCO for IEEE 802.11a WLAN Application. 506-509