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ORCID12. ARC 2016: Mangaratiba, RJ, Brazil
- Vanderlei Bonato
, Christos Bouganis, Marek Gorgon:
Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings. Lecture Notes in Computer Science 9625, Springer 2016, ISBN 978-3-319-30480-9
Invited Talks
- Christoforos Kachris, Dimitrios Soudris, Georgi Gaydadjiev, Huy-Nam Nguyen, Dimitrios S. Nikolopoulos, Angelos Bilas, Neil Morgan, Christos Strydis, Christos Tsalidis, John Balafas, Ricardo Jiménez-Peris, Alexandre Almeida:
The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres. 3-13 - Jones Yudi Mori, André Werner, Arij Shallufa, Florian Fricke, Michael Hübner:
A Design Methodology for the Next Generation Real-Time Vision Processors. 14-25 - Evangelinos P. Mariatos, Christos P. Antonopoulos, Nikolaos S. Voros:
EEG Feature Extraction Accelerator Enabling Long Term Epilepsy Monitoring Based on Ultra Low Power WSNs. 26-37
Video and Image Processing
- José L. Núñez-Yáñez:
Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application. 41-53 - Tomasz Kryjak, Marek Gorgon, Mateusz Komorkiewicz:
An Efficient Hardware Architecture for Block Based Image Processing Algorithms. 54-65 - Abiel Aguilar-González, Miguel O. Arias-Estrada:
An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances. 66-77 - Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger F. Woods, Karen Rafferty:
FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG. 78-90 - Masahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri:
A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human Detection. 91-104 - Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip H. W. Leong, Yu Peng:
A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification. 105-116
Fault-Tolerant Systems
- Yudai Shirakura, Taisei Segawa, Yuichiro Shibata, Kenichi Morimoto, Masaharu Tanaka, Masanori Nobe, Hidenori Maruta, Fujio Kurokawa:
A Redundant Design Approach with Diversity of FPGA Resource Mapping. 119-131 - Jorge L. Tonfat, Lucas A. Tambara, André Flores dos Santos, Fernanda Gusmão de Lima Kastensmidt:
Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors. 132-143 - Leonardo P. Santos, Gabriel L. Nazar, Luigi Carro:
Low Cost Dynamic Scrubbing for Real-Time Systems. 144-156
Tools and Architectures
- Mohammad Tahghighi, Sharad Sinha, Wei Zhang:
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. 159-170 - Karim M. Abdellatif, Christian Cornesse, Jacques J. A. Fournier, Bruno Robisson:
New Partitioning Approach for Hardware Trojan Detection Using Side-Channel Measurements. 171-182 - Bilal Habib, Kris Gaj:
A Comprehensive Set of Schemes for PUF Response Generation. 183-194 - Vitor Coimbra, Marcus Vinicius Lamar:
Design and Optimization of Digital Circuits by Artificial Evolution Using Hybrid Multi Chromosome Cartesian Genetic Programming. 195-206 - Marlon Wijeyasinghe, David Thomas:
A Multi-codec Framework to Enhance Data Channels in FPGA Streaming Systems. 207-219
Signal Processing
- Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira:
Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications. 223-232 - Arthur Spierer, Andres Upegui:
Real-Time Audio Group Delay Correction with FFT Convolution on FPGA. 233-244 - Markus Weinhardt:
Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm. 245-257
Multicore Systems
- Jeckson Dellagostin Souza, João Victor Gomes Cachola, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System. 261-272 - Falco K. Bapp, Oliver Sander, Timo Sandmann, Hannes Stoll, Jürgen Becker:
Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures. 273-286 - Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Zynq Cluster for CFD Parametric Survey. 287-299
Invited Paper on Funded RD Running and Completed Projects Posters
- Konrad Häublein, Christian Hartmann, Marc Reichenbach, Dietmar Fey:
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. 303-311 - Mahnaz Mohammadi, Rohit Ronge, Sanjay Sri Vallabh Singapuram, S. K. Nandy:
Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture. 312-319 - Shreyas G. Singapura, Yi-Hua E. Yang, Anand V. Panangadan, Tamás Németh, Peter Ng, Viktor K. Prasanna:
FPGA-Based Acceleration of Pattern Matching in YARA. 320-327 - Jones Yudi Mori, Frederik Kautz, Michael Hübner:
Efficient Camera Input System and Memory Partition for a Vision Soft-Processor. 328-333 - Bruno da Silva, Jan Lemeire, An Braeken, Abdellah Touhafi:
A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis. 334-342 - Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker:
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. 343-351 - Stephanie Friederich, Niclas Lehmann, Jürgen Becker:
Adaptive Bandwidth Router for 3D Network-on-Chips. 352-360 - James J. Davis, Peter Y. K. Cheung:
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. 361-368
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