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ORCIDASAP 1996: Chicago, IL, USA
- 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA. IEEE Computer Society 1996, ISBN 0-8186-7542-X
Miscellaneous Applications
- Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens:
An Architectural Design For Parallel Fractal Compression. 3-11 - Valerie E. Taylor, Jian Chen, Thomas Canfield, Rick L. Stevens:
A Decomposition Method For Efficient Use Of Distributed Supercomputers For Finite Element Applications. 12-24 - Jeffrey D. Hirschberg, Richard Hughey, Kevin Karplus, Don Speck:
Kestrel: A Programmable Array for Sequence Analysis. 25-34 - Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.:
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. 35-
Arithmetic Algorithms and Architectures
- Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller
:
A New Euclidean Division Algorithm For Residue Number Systems. 45-54 - Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring Cordic Algorithm And Architectures. 55-64 - Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga:
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. 65-71 - Leilei Song, Keshab K. Parhi:
Efficient Finite Field Serial/Parallel Multiplication. 72-
DSP Architectures
- Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods:
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. 83-92 - David A. Parker, Keshab K. Parhi:
Area-Efficient Parallel FIR Digital Filter Implementations. 93-111 - Jan Peter Berns, Tobias G. Noll:
A Flexible Motion Estimation Chip for Variable Size Block Matching. 112-121 - Hangu Yeo, Yu Hen Hu:
A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation. 122-
Systolic Algorithms and Architectures
- Jürgen Teich, Lothar Thiele, Li Zhang:
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. 131-144 - Pascal Faudemay, Laurent Winckel:
An Abstract Model for a Low Cost SIMD Architecture. 145-154 - Hyuk-Jae Lee, José A. B. Fortes:
Automatic Generation of Modular Mappings. 155-164 - Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata:
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. 165-
Poster Session
- Nicolas Hubart:
Monitoring and Debugging a Hard Real-Time Distributed Computer for Aircraft Industry. 175-182 - Shietung Peng, Stanislav Sedukhin, Igor S. Sedukhin:
Parallel Algorithm And Architecture For Two-Step Division-Free Gaussian Elimination. 183-192 - Mohan Vishwanath, Robert Michael Owens:
A Common Architecture For The DWT and IDWT. 193-198 - Guy Even, Ami Litman:
Overcoming chip-to-chip delays and clock skews. 199-208 - Patrick Trane:
Diagnosis Algorithm for Mobility-Oriented System. 209-220 - Minesh I. Patel, N. Ranganathan:
A VLSI System Architecture For Real-Time Intelligent Decision Making. 221-230 - Arthur Wang, Kung Yao, Ralph E. Hudson, Daniel Korompis, Flavio Lorenzelli, Sigfrid D. Soli, Shawn X. Gao:
Microphone Array for Hearing Aid and Speech Enhancement Applications. 231-239 - David R. Surma, Edwin Hsing-Mean Sha:
Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems. 240-249 - Daping Song, Thierry Divoux, Francis LePage:
Design of the Distributed Architecture of a Machine-tool Using FIP Fieldbus. 250-
Design Methodologies
- Karl M. Fant, Scott A. Brandt:
NULL Convention LogicTM: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis. 261-273 - Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures. 274-283 - David R. Smith:
Hardware Synthesis From Encapsulated Verilog Modules. 284-
Rapid Prototyping
- Bradly K. Fawcett, J. Watson:
Reconfigurable Processing With Field Programmable Gate Arrays. 293-302 - Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri:
Rapid Prototyping of Reconfigurable Coprocessors. 303-312 - Jeffrey Walrath:
Performance Modeling and Tradeoff Analysis During Rapid Prototyping. 313-322 - Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere:
Jacobi-Specific Processor Arrays. 323-
Compilers I
- James E. Beck, Daniel P. Siewiorek:
A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task Allocation. 342-352 - Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien:
On the Removal of Anti and Output Dependences. 353-364 - Shuvra S. Bhattacharyya, Sundararajan Sriram, Edward A. Lee:
Latency-constrained Resynchronization for Multiprocessor DSP Implementation. 365-380 - Florent de Dinechin, Sophie Robert:
Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. 381-
Compilers II
- Patrice Quinton, Sanjay V. Rajopadhye, Tanguy Risset:
Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains. 391-401 - Edin Hodzic, Weijia Shang:
On Supernode Transformation with Minimized Total Running Time. 402-414 - Philippe Clauss, Vincent Loechner:
Parametric Analysis of Polyhedral Iteration Spaces. 415-
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