default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID35th ASAP 2024: Hong Kong
- 35th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2024, Hong Kong, July 24-26, 2024. IEEE 2024, ISBN 979-8-3503-4963-4
- Frederik Kautz
, Sven Gesper, Gia Bao Thieu, Hans-Martin Blüthgen, Holger Blume, Guillermo Payá-Vayá:
Multi-Level Prototyping of a Vertical Vector AI Processing System. 1-2 - Valentin Isaac-Chassande, Adrian Evans, Yves Durand, Frédéric Rousseau:
SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix Kernels. 3-7 - Yannick Braatz, Taha Soliman, Shubham Rai, Dennis Sebastian Rieber, Oliver Bringmann:
CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions. 8-16 - Jiangnan Li, Yazhou Yan, Guowei Zhu, Wenbo Yin, Lingli Wang:
An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs. 17-18 - Yuanhai Zhang, Shuai Zhao, Gang Chen, Kai Huang:
Fault-tolerant DAG Scheduling with Runtime Reconfiguration on Multicore Real-Time Systems. 19-27 - Oliver Renke, Christoph Riggers, Jens Karrenbauer, Holger Blume:
Design Space Exploration of Semantic Segmentation CNN SalsaNext for Constrained Architectures. 28-29 - Hongbin Wang, Yi Zou, Guohua Wen, Junfeng Hu:
Memory Access Acceleration Through Architecture Design for Edge SoCs. 30-31 - Tenghao Zhao, Zhaohui Ye:
ZeroVex: A Scalable and High-performance RISC-V Vector Processor Core for Embedded Systems. 32-33 - Yingchang Mao, Qiang Liu, Ray C. C. Cheung:
MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training. 34-35 - Yasong Cao, Mei Wen, Junzhong Shen, Zhongxing Li:
BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM. 36-44 - Songqiao Cui, Josep Balasch:
Configurable Loop Shuffling via Instruction Set Extensions. 45-53 - Haoran Su, Nan Wu:
Deoxys: Defensive Approximate Computing for Secure Graph Neural Networks. 54-60 - Yang Yang, Rajgopal Kannan, Viktor K. Prasanna:
A Framework for Generating Accelerators for Homomorphic Encryption Operations on FPGAs. 61-70 - Yao Liu, Shiyang Chen, Long Ma, Guolong Yang, Kun Wan:
Real-Time Order Book Building and Snapshot Generating for High Frequency Trading on FPGA. 71-76 - Yuchen Gui, Qizhe Wu, Wei Yuan, Huawen Liang, Xiaotian Wang, Xi Jin:
A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling. 77-78 - Haifeng Sun, Yunfeng Deng:
A DRL-Based Multi-Priority Task Division Scheduling Strategy in IIoT. 79-87 - Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Qing Yang, Tao Wei:
TwinStep Network (TwNet): a Neuron-Centric Architecture Achieving Rapid Training. 88-96 - Dominik Walter, Thomas Adamtschuk, Frank Hannig, Jürgen Teich:
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. 97-106 - Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk:
Accelerating MRI Uncertainty Estimation with Mask-Based Bayesian Neural Network. 107-115 - Yude Fang, Junhui Wang, Libo Huang, Yongwen Wang, Weixia Xu:
Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor. 116-117 - Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch:
SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay. 118-119 - Uyong Lee, Yeji Park, Junsu Heo, Sungkyung Park, Chester Sungchung Park:
Design Space Exploration of FFT Accelerators for IEEE 802.11ax using High-Level Synthesis. 120-121 - Shengbai Luo, Bo Wang, Yihao Shi, Xueyi Zhang, Qingshan Xue, Sheng Ma:
Sparm: A Sparse Matrix Multiplication Accelerator Supporting Multiple Dataflows. 122-130 - Junzhe Huang, Qiang Dou, Li Shen:
Extending the RISC-V Instruction Set for High Performance Data Compression Hardware Acceleration. 131-132 - Shaoyang Sun, Boyin Jin, Jiahang Lou, Jiangnan Li, Yuhang Cao, Jingyuan Li, Chen Shen, Yuan Dai, Wenbo Yin, Wai-Shing Luk, Lingli Wang:
MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes. 133-134 - Zhuoheng Ran, Muhammad A. A. Abdelgawad, Zekai Zhang, Ray C. C. Cheung, Hong Yan:
RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications. 135-142 - Paul Delestrac, Jonathan Miquel, Debjyoti Bhattacharjee, Diksha Moolchandani, Francky Catthoor, Lionel Torres, David Novo:
Analyzing GPU Energy Consumption in Data Movement and Storage. 143-151 - Shinya Miura, Qiong Chang, Jun Miyazaki:
$k$-Way In-Place Merge by CPU-GPU Cooperative Processing. 152-160 - Yiyang Lin, Yi Zou, Yanfeng Yang:
CSIFA: A Configurable SRAM-based In-Memory FFT Accelerator. 161-162 - Hanqing Liu, Xiaole Cui, Sunrui Zhang, Mingqi Yin, Yuanyuan Jiang, Xiaoxin Cui:
A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. 163-171 - Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini:
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. 172-173 - Shipeng Yue, Honghao Liang, Xinpeng Xing, Haigang Feng:
SLICE Matrix: A Memory Access Scheduling Policy for Multicore Network Processors. 174-175 - Jens Karrenbauer, Sven Schönewald, Simon C. Klein, Holger Blume:
Enhancing a Hearing Aid Processor with ISA Extensions Supporting Flexible Fixed-Point Formats. 176-183 - Tianyi Yu, Omar Ragheb, Stephen Wicklund, Jason Helge Anderson:
MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for CGRAs. 184-192 - Zekai Zhang, Ray Chak-Chung Cheung:
Design of Light-Weight Encryption Algorithm Based on RISC-V Platform: (PhD Forum Paper). 193-194 - Salim Khemira, Xinyuan Wang, Anh Nguyen, Yutaka Tamiya, Makoto Taiji, Takahide Yoshikawa, Jason Helge Anderson:
Raising Compute Density of Molecular Dynamics Simulation Through Approximate Memoization. 195-203 - Mohamed Bouaziz, Suhaib A. Fahmy:
Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper). 204-205 - Georg Rutishauser, Joan Mihali, Moritz Scherer, Luca Benini:
xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems. 206-213 - Qingchen Zhai, Zhiwei Zhang, Ruozhou Xiao:
LLM Based End-to-end Branch Predictor Optimization Generator. 214-216 - Andreas Böttcher, Martin Kumm:
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs. 217-225 - Annina Gutermann, Jürgen Becker:
A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper). 226-227 - Dhruv Gajaria, Tosiron Adegbija, Kevin Antony Gomez:
CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing. 228-236 - Dong-eon Won, Yeeun Kim, Janghwan Lee, Minjae Lee, Jonghyun Bae, Jongjoo Park, Jeongyong Song, Jungwook Choi:
ISP2DLA: Automated Deep Learning Accelerator Design for On-Sensor Image Signal Processing. 237-238 - Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe:
Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI. 239-240 - Mateusz Wygrzywalski, Robert Szczygiel:
Lightweight Extension of RISC-V Core for NTT-like Algorithms: (PhD Forum Paper). 241-242 - Tao Cai, Jianfei Dai, Dejiao Niu, Lei Li, Zeyu Huang, Qiangqiang Ni:
A LLC-Friendly LSM-tree. 243-244 - Kangli Zhao, Anping He, Di Zhao:
Research on High-Efficiency Asynchronous Superscalar Processors: (PhD Forum Paper). 245-246 - Xiqin Tang, Delong Shang:
Design of High-Performance while Energy-Efficient Microprocessor with Novel Asynchronous Techniques: (PhD Forum Paper). 247-248
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-10-17 00:40 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated, funded, and maintained by:
Schloss Dagstuhl - Leibniz Center for Informatics is a member of the Leibniz Association and is funded by the federal government of Germany and the states of Germany, especially Saarland and Rhineland‑Palatinate.
