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ORCID28th ASYNC 2023: Beijing, China
- 28th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2023, Beijing, China, July 16-19, 2023. IEEE 2023, ISBN 979-8-3503-0576-0
- Prafull Purohit
, Johannes Leugering, Rajit Manohar:
An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. 1-10 - Carsten Nielsen, Zhe Su, Giacomo Indiveri:
Yak: An Asynchronous Bundled Data Pipeline Description Language. 34-41 - Dexuan Huo, Jilin Zhang, Jian Zhang, Hong Chen:
A 28nm Energy-efficient Asynchronous SNN Accelerator with On-chip Learning for Gas Recognition. 42-47 - Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné:
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. 58-59 - Mackenzie J. Wibbels, Baudouin Chauviere, Kenneth S. Stevens:
Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms. 60-70 - Venkata Nori, Baudouin Chauviere, Mackenzie J. Wibbels, Kenneth S. Stevens:
A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling. 71-77 - Rajit Manohar, Yoram Moses:
Timed Signalling Processes. 10-19 - Jilin Zhang, Chunqi Qian, Dexuan Huo, Jian Zhang, Hong Chen:
Designing Self-timed Asynchronous Circuits with Chisel. 27-33 - Zhe Su, Hyunjung Hwang, Tristan Torchet, Giacomo Indiveri:
Core Interface Optimization for Multi-core Neuromorphic Processors. 89-98 - Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer:
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. 48-57 - Xiang Wu, Rajit Manohar:
Verification-Driven Design for Asynchronous VLSI. 78-88 - Cole Sherrill, Kyle Orman, Nicholas Brown, Jia Di:
Case Study for Skewing MTNCL Circuits. 20-26 - Karthi Srinivasan, Yoram Moses, Rajit Manohar:
Opportunistic Mutual Exclusion. 1-9 - Ebelechukwu Esimai, Marly Roncken:
Flexible Compilation and Refinement of Asynchronous Circuits. 109-119
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