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ORCID16th DAC 1979: San Diego, California, USA
- David W. Hightower:
Proceedings of the 16th Design Automation Conference, DAC '79, San Diego, California, USA, June 25-27, 1979. ACM 1979 - Ulrich Lauther:
A min-cut placement algorithm for general cell assemblies based on a graph representation. 1-10 - Satoshi Goto:
A two-dimensional placement algorithm for the master slice LSI layout problem. 11-17 - Shinichi Murai, Hiroo Tsuji, Morio Kakinuma, Kazumichi Sakaguchi, Chiyoji Tanaka:
A hierarchical placement procedure with a simple blocking scheme. 18-23 - Edward P. Stabler, Victor M. Kureichik, Valery A. Kalashnikov:
Placement algorithm by partitioning for optimum rectangular placement. 24-25 - Harold W. Carter, Melvin A. Breuer, Zahir A. Syed:
Incremental processing applied to Steinberg's placement procedure. 26-31 - Wayne E. Carlson, Richard E. Parent, Charles A. Csuri:
The use of color and 3-D temporal and spatial data management techniques in computer-aided design. 32-38 - B. Meyer:
A low cost satellite for fast interactive graphics in a time-sharing environment. 39-44 - Yaohan Chu:
Concepts of a microcomputer design language. 45-52 - Gerhard Zimmermann:
The MIMOLA design system a computer aided digital processor design method. 53-58 - Peter Marwedel:
The MIMOLA design system: Detailed description of the software system. 59-63 - Mario Barbacci:
Instruction set processor specifications for simulation, evaluation, and synthesis. 64-72 - Alice C. Parker, Donald E. Thomas, Daniel P. Siewiorek, Mario Barbacci, Louis J. Hafer, Gary W. Leive, Jinchoon Kim:
The CMU design automation system: An example of automated data path design. 73-80 - Carl R. McCaw:
Unified Shapes Checker - a checking tool for LSI. 81-87 - Toshiro Akino, Masafumi Shimode, Yukinaga Kurashige, Toshio Negishi:
Circuit simulation and timing verification based on MOS/LSI mask information. 88-94 - C. S. Chang:
LSI layout checking using bipolar device recognition technique. 95-101 - Herman Beke, Willy Sansen:
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI. 102-108 - K. W. Lallier, R. K. Jackson:
A new circuit placement program for FET chips. 109-113 - Mitsuo Ishii, Masanari Yamamoto, Michiko Iwasaki, Hiroshi Shiraishi:
An experimental input system of hand-drawn logic circuit diagram for LSI CAD. 114-120 - Yoshio Matsui, Hironori Takagi, Shigekazu Emori, Norio Masuda, Shohei Sasabe, Chuzo Yoshimura, Toshikazu Shirai, Susumu Nioh, Bunzi Kinno:
Automatic pipe routing and material take-off system for chemical plant. 121-127 - Chris I. Yessios:
Stonewalls: Experiments in intelligent drafting. 128-134 - Nicholas H. Weingarten, William Kovacs, Michael Corden:
DRAW3D: Time sharing graphic interaction using a device-space buffer. 135-141 - Marc Schiler, Donald P. Greenberg:
Computer simulation of foliage shading in building energy loads. 142-148 - Charles W. Cha:
Multiple fault diagnosis in combinational networks. 149-155 - John Grason:
TMEAS, a testability measurement program. 156-161 - Yacoub M. El-Ziq:
Testing of MOS combinational networks a procedure for efficient fault simulation and test generation. 162-170 - William A. Johnson:
Behavioral-level test development. 171-179 - Eskil Kjelkerud, Owe Thessén:
Generation of hazard free tests using the D-algorithm in a timing accurate system for logic and deductive fault simulation. 180-184 - Lawrence A. O'Neill, C. G. Savolaine, T. J. Thompson, Jeffery M. Franke, Robert A. Friedenson, E. D. Walsh, Patricia H. McDonald, J. R. Breiland, D. S. Evans:
Designers Workbench - efficient and economical design aids. 185-199 - Kenneth Preiss:
A procedure for checking the topological consistency of a 2-D or 3-D finite element mesh. 200-206 - David F. Rogers, Francisco A. Rodriguez, Steven G. Satterfield:
Computer Aided Ship Design and numerically controlled production of towing tank models. 207-214 - Edward J. Bresnen:
Automation of manufacturing planning, shop loading and work measurement in an engineering job shop environment. 215-221 - Larry Lichten:
A partial solution to fitting large parametric surfaces in computer-aided design systems. 222-228 - H. Y. Hsieh, N. B. Rabbat:
Macrosimulation with Quasi-general Symbolic FET Macromodel and Functional Latency. 229-234 - Eskil Kjelkerud, Owe Thessén:
Methods of modelling digital devices for logic simulation. 235-241 - Philip S. Wilcox:
Digital logic simulation at the gate and functional level. 242-248 - Will Sherwood:
A hybrid scheduling technique for hierarchical logic simulators or "Close Encounters of the Simulated Kind". 249-254 - Zainalabedin Navabi, Fredrick J. Hill:
Efficient simulation of AHPL. 255-262 - Norbert Giambiasi, A. Miara, D. Muriach:
SILOG: A practical tool for large digital network simulation. 263-271 - Dwight D. Hill, William M. van Cleemput:
SABLE: A tool for generating structured, multi-level simulations. 272-279 - William C. Carter, William H. Joyner Jr., Daniel Brand:
Symbolic simulation for correct machine design. 280-286 - Takao Uehara, William M. van Cleemput:
Optimal layout of CMOS functional arrays. 287-289 - Tatsuya Kawamoto, Yoji Kajitani:
The minimum width routing of A 2-row 2-layer polycell-layout. 290-296 - Koji Sato, Takao Nagai, Hiroyoshi Shimoyama, Toshihiko Yahara:
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks. 297-304 - John P. Gray:
Introduction to silicon compilation. 305-306 - Ron Ayres:
IC specification language. 307-309 - Dave Johannsen:
Bristle Blocks: A silicon compiler. 310-313 - Ron Ayres:
Silicon compilation-a hierarchical use of PLAs. 314-326 - Pao Tsin Wang, Paul Bassett:
A software system for Automated Placement And Wiring of LSI chips. 327-329 - Tom C. Bennett, Kim R. Stevens, William M. van Cleemput:
Dynamic design rule checking in an interactive printed circuit editor. 330-336 - David R. Johnson:
PC board layout techniques. 337-343 - Patricia H. McDonald:
The real world of design automation - part II or adapting to the joys of madness (Panel Session). 344-345 - Michael J. Cronin:
"Views of a vendor" (Position Paper). 346 - J. B. Kane:
Design Automation concerns (Position Paper). 347-348 - Paul Losleben:
Future of design automation (Position Paper). 349 - Waldo George Magnuson Jr.:
Moving a D.A. system from development to production (Position Paper). 350-351 - Donald L. Peterson:
Design Automation philosophies (Position Paper). 352 - Sany M. Leinwand, T. Lamdan:
Design verification based on functional abstraction. 353-359 - Nobuaki Kawato, Takao Saito, Fumihiro Maruyama, Takao Uehara:
Design and verification of large-scale computers by using DDL. 360-366 - Yasuhiro Ohno, Masayuki Miyoshi, Katsuya Sato:
Logic verification system for very large computers using LSI's. 367-374 - John A. Darringer:
The application of program verification techniques to hardware verification. 375-381 - Jerry T. Harvel:
Cost effective data entry techniques for design automation. 382 - Faik S. Ozdemir:
Electron beam lithography. 383-391 - R. R. Rath:
Hughes S&CG custom LSI layouts - 'we did it our way'. 392-397 - Stanley Wong, W. A. Bristol:
A Computer-Aided Design data base. 398-402 - Robert I. Gardner, Paul B. Weil:
Hierarchical modeling and simulation in VISTA. 403-405 - Lorretta I. Corrigan:
A placement capability based on partitioning. 406-413 - Daniel J. Sucher, Donald F. Wann:
A design aids data base for digital components. 414-420 - Edward Marlow Hoskins:
Descriptive databases in some design/manufacturing environments. 421-436 - Kuo-Yen Nieng, Dennis A. Beckley:
Component library for an integratel DA system. 437-444 - James A. Wilmore:
The design of an efficient data base to support an interactive LSI layout system. 445-451 - M. F. Oakes:
The complete VLSI design system. 452-460 - Paul Losleben, Kathryn Thompson:
Topological analysis for VLSI circuits. 461-473 - Bryan Preas, William M. van Cleemput:
Placement algorithms for arbitrarily shaped blocks. 474-480 - Jirí Soukup:
Global router. 481-484 - S. Pimont:
New algorithms for grid-less routing of high density printed circuit boards. 485 - John C. Foster:
A "lookahead" router for multilayer printed wiring boards. 486-493 - Lawrence Dysart, Mikhail Koifman:
An application of branch and bound method to automatic printed circuit board routing. 494-499 - Ola A. Marvik:
An interactive routing program with On-line clean-up of sketched routes. 500-505 - Ken-ichi Sahara, Ken-ichi Kobori, Ikuo Nishioka:
An interactive layout system of analog printed wiring boards. 506-512 - Frederic I. Parke:
An introduction to the N. mPc design environment. 513-519 - Charles W. Rose, Larry A. Rogers, Ralph Straubs:
The N. mPc system description facility. 520-528 - Frederic I. Parke, Donald C. Hewitt Jr., Charles W. Rose:
The N.mPc runtime environment. 529-536 - Gregory M. Ordy, Frederic I. Parke:
An evaluation of the N. mPc design environment. 537-542 - David Gibson:
Can C.A.D. meet the VLSI design problems of the 80's?(Panel Discussion). 543 - David Giuliani:
Will Disign tools catch up to VLSI design. 544-545 - Ronald Waxman:
VLSI - a design challenge. 546-547 - Bill Lattin:
VLSI design methodology the problem of the 80's for microprocessor design. 548-549 - Warren Wiemann:
CAD system for VLSI. 550 - Robert P. Larsen:
Can CAD meet the VLSI design problems of the 80's? 551 - David W. Hightower:
Can CAD meet the VLSI design problems of the 80's. 552-553 - William M. van Cleemput:
Computer hardware description languages and their applications. 554-560 - Lionel Bening:
Developments in computer simulation of gate level physical logic. 561-567
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