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ORCID22nd DAC 1985: Las Vegas, Nevada, USA
- Hillel Ofek, Lawrence A. O'Neill:
Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985. ACM 1985, ISBN 0-8186-0635-5 - Tariq Samad, Stephen W. Director:
Towards a natural language interface for CAD. 2-8 - Alberto Di Janni, Margherita Italiano:
Unified user interface for a CAD system. 9-15 - Cyrus Bamji, Charles E. Hauck, Jonathan Allen:
A design by example regular structure generator. 16-22 - S. C. Hughes, D. B. Lewis, C. J. Rimkus:
A technique for distributed execution of design automation tools. 23-30 - Ellen J. Yoffa, Peter S. Hauge:
ACORN: a local customization approach to DCVS physical design. 32-38 - Tak-Kwong Ng, S. Lennart Johnsson:
Generation of layouts from MOS circuit schematics: a graph theoretic approach. 39-45 - Shigeo Noda, Hitoshi Yoshizawa, Etsuko Fukuda, Haruo Kato, Hiroshi Kawanishi, Takashi Fujii:
Automatic layout algorithms for function blocks of CMOS gate arrays. 46-52 - Gabriele Saucier, Ghislaine Thuau:
Systematic and optimized layout of MOS cells. 53-61 - C. Durward Rogers, Jonathan B. Rosenberg, Stephen W. Daniel:
MCNC's vertically integrated symbolic design system. 62-68 - George Entenman, Stephen W. Daniel:
A fully automatic hierarchical compactor. 69-75 - Phillip Smtih, Stephen W. Daniel:
The VIVID system approach to technology independence: the matster technology file system. 76-81 - Jonathan B. Rosenberg:
Auto-interactive schematics to layout translation. 82-87 - Al Lowenstein, Greg Winter:
Importance of standards (tutorial session). 88-93 - Roger J. Pachter:
Computer aided (CA) tools integration and related standards development in a multi-vendor universe (panel session). 94-95 - John A. Pierro, George F. Donnellan:
Mechanical design/analysis integration on Apollo workstations. 96-101 - Raj Abraham:
Custom microcomputers for CAD optimization software. 102-110 - Yehuda E. Kalay:
A database management approach to CAD/CAM systems integration. 111-116 - Malgorzata Marek-Sadowska:
Two-dimensional router for double layer layout. 117-123 - Michael Burstein, Mary N. Youssef:
Timing influenced layout design. 124-130 - J. N. Song, Y. K. Chen:
An algorithm for one and half layer channel routing. 131-136 - B. Hennion, P. Senn, D. Coquelle:
A new algorithm for third generation circuit simulators: the one-step relaxation method. 137-143 - Mark D. Matson:
Macromodeling of digital MOS VLSI Circuits. 141-151 - Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa:
ACTAS: an accurate timing analysis system for VLSI. 152-158 - Cecelia Jankowski:
Engineering workstation applications to systems design (panel session): life above the IC. 159-160 - J. P. Simmons Jr.:
Early verification of prototype tooling for IC designs (tutorial). 161 - Steven T. Healey, Daniel D. Gajski:
Decomposition of logic networks into silicon. 162-168 - Christopher Rowen, John L. Hennessy:
SWAMI: a flexible logic implementation system. 169-175 - David E. Krekelberg, Gerald E. Sobelman, Chu S. Jhon:
Yet another silicon compiler. 176-182 - José Monteiro da Mata:
ALLENDE: a procedural language for the hierarchical specification of VLSI layouts. 183-189 - Hingsam S. Fung, Sanford Hirschhorn, R. Kulkarni:
Design for testability in a silicon compilation environment. 190-196 - Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli:
PLATYPUS: a PLA test pattern generation tool. 197-203 - Hans-Joachim Wunderlich:
PROTEST: a tool for probabilistic testability analysis. 204-211 - Takuji Ogihara, Shuichi Saruyama, Shinichi Murai:
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits. 212-218 - Prathima Agrawal, Frederick L. Cohen, Chet A. Palesko, Hung-Fai Stephen Law, Mark Miller, Mike Price, David W. Smith, Nicholas P. Van Brunt:
Workstations (panel discussion): a complete solution to the VLSI designer? 219-225 - Francine S. Frome:
Course, video, and manual dexterity (tutorial): tailoring training to CAD users. 226-231 - Timothy Blackman, Jeffrey R. Fox, Christopher Rosebrugh:
The Silc silicon compiler: language and features. 232-237 - F. Meshkinpour, Milos D. Ercegovac:
A functional language for description and design of digital systems: sequential constructs. 238-244 - Warren E. Cory:
Layla: a VLSI layout language. 245-251 - Thaddeus J. Kowalski, Donald E. Thomas:
The VLSI design automation assistant: what's in a knowledge base. 252-258 - Melvin A. Breuer, Xi-an Zhu:
A knowledge based system for selecting a test methodology for a PLA. 259-265 - Rostam Joobbani, Daniel P. Siewiorek:
WEAVER: a knowledge-based routing expert. 266-272 - Neil Bergmann:
Generalised CMOS-a technology independent CMOS IC design style. 273-278 - Kung-Chao Chu, Y. Edmund Lien:
Technology tracking for VLSI layout design tools. 279-285 - Walter S. Scott, John K. Ousterhout:
Magic's circuit extractor. 286-292 - Louis Scheffer, Ronny Soetarman:
Hierarchical analysis of IC artwork with user defined abstraction rules. 293-298 - George E. Bier, Andrew R. Pleszkun:
An algorithm for design rule checking on a multiprocessor. 299-304 - Erich Barke:
Resistance calculation from mask artwork data by finite element method. 305-311 - Thomas R. Smith:
A data architecture for an uncertain design and manufacturing environment. 312-318 - Andrzej J. Strojwas:
CMU-CAM system. 319-325 - Keith S. Reid-Green:
Cost-effective computer-aided manufacturing of prototype parts. 326-329 - Kai-Hsiung Chang, William G. Wee:
A knowledge based planning system for mechanical assembly usign robots. 330-336 - Susan L. Taylor, Roderic Beresford, Theodore Sabety:
Layout design-lessons from the Jedi designer (tutorial session). 337 - Winfried Hahn, Kristian Fischer:
MuSiC: an event-flow computer for fast simulation of digital systems. 338-344 - David M. Lewis:
A hardware engine for analogue mode simulation of MOS digital circuits. 345-351 - Patrick M. Hefferan, Robert J. Smith, Val Burdick, Donald L. Nelson:
The STE-264 accelerated electronic CAD system. 352-358 - Philip M. Spira, Carl Hage:
Hardware acceleration of gate array layout. 359-366 - Jayanth V. Rajan, Donald E. Thomas:
Synthesis by delayed binding of decisions. 367-373 - Robert L. Blackburn, Donald E. Thomas:
Linking the behavioral and structural dominis of representation in a synthesis system. 374-380 - Kumar Ramayya, Anshul Kumar, Surendra Prasad:
An automated data path synthesizer for a canonic structure, implementable in VLSI. 381-387 - Anjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra:
Automatic generation of digital system schematic diagrams. 388-395 - Y. Eric Cho:
A subjective review of compaction (tutorial session). 396-404 - Michael R. Wayne, Susan M. Braun:
Looking for Mr. "Turnkey". 405-409 - Marianne Winslett Wilkins, Richard Berlin, Thomas H. Payne, Gio Wiederhold:
Relational and entity-relationship model databases and specialized design files in VLSI design. 410-416 - Connie U. Smith, Geoffrey A. Frank, John L. Cuadrado:
An architecture design and assessment system for software/hardware codesign. 417-424 - Steve Perry, Mike Mitchell, David J. Pilling:
Yield analysis modeling. 425-428 - Takeshi Sakata, Aritoyo Kishimoto:
A circuit comparison system for bipolar linear LSI. 429-434 - Russel L. Steinweg, Susan J. Aguirre, Kerry Pierce, Scott Nance:
Silicon compilation of gate array bases. 435-438 - M. Iachponi, D. Vail, S. Bierly, A. Ignatowski:
A hierarchical gate array architecture and design methodology. 439-442 - C. P. Hsu, B. N. Tien, K. Chow, R. A. Perry, J. Tang:
ALPS2: a standard cell layout system for double-layer metal technology. 443-448 - Hart Anway, Greg Farnham, Rebecca Reid:
PLINT layout system for VLSI chips. 449-452 - Robert A. Walker, Donald E. Thomas:
A model of design representation and synthesis. 453-459 - Norbert Giambiasi, B. MacGee, R. L'Bath, L. Demians d'Archimbaud, C. Delorme, P. Roux:
An adaptive and evolutive tool for describing general hierarchical models, based on frames and demons. 460-467 - James C. Althoff, Robert D. Shur:
A behavioral modeling system for cell compilers. 468-474 - Raul Camposano:
Synthesis techniques for digital systems design. 475-481 - Charles W. Rose, Marcus Buchnen, Yatin Trivedi:
Integrating stochastic performance analysis with system design tools. 482-488 - Nohbyung Park, Alice C. Parker:
Synthesis of optimal clocking schemes. 489-495 - Rob A. Rutenbar:
Future directions for DA machine research (panel session). 496-497 - Robert P. Collins, William J. Ketelhut:
The impact of technological advances on programmable controller s(tutorial session). 498-502 - Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa:
A routing procedure for mixed array of custom macros and standard cells. 503-508 - A. C. Finch, K. J. Mackenzie, G. J. Balsdon, G. Symonds:
A method for gridless routing of printed circuit boards. 509-515 - Sangyong Han, Sartaj Sahni:
Layering algorithms for single row routing. 516-522 - Robert Leonard Joseph:
An expert systems approach to completing partially routed printed circuit boards. 523-528 - W. M. Budney, S. K. Holewa:
MIDAS: integrated CAD for total system design. 529-535 - Shigenobu Suzuki, Kazutoshi Takahashi, Takao Sugimoto, Mikio Kuwata:
Integrated design system for supercomputer SX-1/SX-2. 536-542 - Anthony F. Hutchings, Richard J. Bonneau, William M. Fisher:
Integrated VLSI CAD systems at Digital Equipment Corporation. 543-548 - N. J. Elias, R. J. Byrne, A. D. Close, Robert M. McDermott:
The ITT VLSI design system: CAD integration in a multi-national environment. 549-553 - John Lowell:
Computer aided design for analog applications (panel session): an assessment. 554 - E. Ted Grinthal:
Software quality assurance for CAD (tutorial). 555-561 - Christopher W. Pidgeon, Peter A. Freeman:
Development concerns for a software design quality expert system. 562-568 - Howard B. Schutzman:
ICHABOD: a data base manager for design automation applications. 569-576 - G. P. Barabino, G. S. Barabino, G. Bisio, Michele Marchesi:
A module for improving data access and management in an integrated CAD environment. 577-583 - Gary B. Goates, Patrick M. Hefferan, Robert J. Smith, Randy Harris:
Star's envoling design environment: a user's perspective on CAE. 584-590 - Natalie Royal, John Hunter, Irene Buchanan:
A case study in process independence. 591-596 - John P. Gray, John Hunter:
Portability in silicon CAE. 597-601 - Lu Sha, Robert W. Dutton:
An analytical algorithm for placement of arbitrarily sized rectangular blocks. 602-608 - John P. Blanks:
Near-optimal placement using a quadratic objective function. 609-615 - Gotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi:
Knowledge-based placement technique for printed wiring boards. 616-622 - C. Roy, Louis-Philippe Demers, Eduard Cerny, Jan Gecsei:
An object-oriented swicth-level simulator. 623-629 - Richard H. Lathrop, Robert S. Kirk:
An extensible object-oriented mixed-mod functional simulation system. 630-636 - V. Ashok, Roger L. Costello, P. Sadayappan:
Modeling switch-level simulation using data flow. 637-644 - Robert V. Zara, David R. Henke:
Building a layered database for design automation. 645-651 - Paul McLellan:
Effective data management for VLSI design. 652-657 - Eric Schell, M. Ray Mercer:
CADTOOLS: a CAD algorithm development system. 658-666 - Michel R. Dagenais, Vinod K. Agarwal, Nicholas C. Rumin:
The McBOOLE logic minimizer. 667-673 - Prathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas:
Multiple output minimization. 674-680 - Kye S. Hedlund:
Electrical optimization of PLAs. 681-687 - Randal E. Bryant:
Symbolic manipulation of Boolean functions using a graphical representation. 688-694 - Yiwan Wong:
Hierarchical circuit verification. 695-701 - J. Doug Tygar, Ron Ellickson:
Efficient netlist comparison using hierarchy and randomization. 702-708 - Nandakumar N. Tendolkar:
Analysis of timing failures due to random AC defects in VLSI modules. 709-714 - Randal E. Bryant, Michael Dd. Schuster:
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator. 715-719 - Anil K. Gupta, James R. Armstrong:
Functional fault modeling and simulation for VLSI devices. 720-726 - John J. Granacki, David Knapp, Alice C. Parker:
The ADAM advanced design automation system: overview, planner and natural language interface. 727-730 - Gotaro Odawara, Masahiro Tomita, Ichiro Ogata:
Diagrammatic function description of microprocessor and data-flow processor. 731-734 - Edward H. Frank:
Switch-level simulation of VLSI using a special-purpose data-driven computer. 735-738 - Peter J. M. van Laarhoven, Emile H. L. Aarts, Marc Davio:
PHIPLA-a new algorithm for logic minimization. 739-743 - Yue-Sun Kuo, C. Chen, T. C. Hu:
A heuristic algorithm for PLA block folding. 744-747 - Surendra Nahar, Sartaj Sahni, Eugene Shragowitz:
Experiments with simulated annealing. 748-752 - Robert V. Zara, Kevin Rose, Ghulam Nurie, Harish Sarin:
An abstract machine data structure for non-procedural functional models. 753-756 - Vighneswara Row Mokkarala, Antony Fan, Ravi Apte:
A unified approach to simulation and timing verification at the functional level. 757-761 - Thomas J. Schaefer:
A transistor-level logic-with-timing simulator for MOS circuits. 762-765 - Yoshiyuki Koseki, Teruhiko Yamada:
PLAYER: a PLA design system for VLSI's. 766-769 - Robert Dwyer, Stephen Morris, Edward Bard, Daniel Green:
The integration of an advanced gate array router into a fully automated design system. 770-772 - Louise T. Lemaire:
GAMMA: a fast prototype design, build, and test process. 773-776 - Dwight D. Hill, John P. Fishburn, Mary Diane Palmer Leland:
Effective use of virtual grid compaction in macro-module generators. 777-780 - William H. Kao, Nader Fathi, Chia-Hao Lee:
Algorithms for automatic transistor sizing in CMOS digital circuits. 781-784 - Hiroshi Andou, Ichiro Yamamoto, Yuuko Mori, Yutaka Koike, Kimikatsu Shouji, Kazuyuki Hirakawa:
Automatic routing algorithm for VLSI. 785-788 - Stef van Vlierberghe, Jeff Rijmenants, Walter Heyns:
Symbolic hierarchical artwork generation system. 789-793 - Salim U. Chowdhury, Melvin A. Breuer:
The construction of minimal area power and ground nets for VLSI circuits. 794-797 - Fred W. Obermeier, Randy H. Katz:
PLA driver selection: an analytic approach. 798-802 - Semyon Shteingart, Andrew W. Nagle, John Grason:
RTG: automatic register level test generator. 803-807 - Andrzej Krasniewski, Alexander Albicki:
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. 808-811 - Masayuki Miyoshi, Yoshiharu Kazama, Osamu Tada, Yasuo Nagura, Nobutaka Amano:
Speed up techniques of logic simulation. 812-815