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ORCID25th DAC 1988: Anaheim, CA, USA
- Dennis W. Shaklee, A. Richard Newton:
Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988. ACM 1988 - Ian M. Ross:
Future Developments in Information Technology (abstract). 1 - A. Richard Newton:
Twenty-Five Years of Electronic Design Automation. 2 - Charles E. Stroud:
An Automated BIST Approach for General Sequential Logic Synthesis. 3-8 - Kwanghyun Kim, Joseph G. Tront, Dong Sam Ha:
Automatic Insertion of BIST Hardware Using VHDL. 9-15 - Catherine H. Gebotys, Mohamed I. Elmasry:
VLSI Design Synthesis with Testability. 16-21 - Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth:
A Defect-Tolerant and Fully Testable PLA. 22-33 - Ramón D. Acosta, Mark Alexandre, Gary Imken, Bill Read:
The Role of VHDL in the MCC CAD System. 34-39 - David R. Coelho:
VHDL: A Call for Standards. 40-47 - Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu:
Verification of VHDL Designs Using VAL. 48-53 - Xinghao Chen, Michael L. Bushnell:
A Module Area Estimator for VLSI Layout. 54-59 - Gerhard Zimmermann:
A New Area and Shape Function Estimation Technique for VLSI Layouts. 60-65 - Shmuel Wimer, Israel Koren, Israel Cederbaum:
Optimal Aspect Ratios of Building Blocks in VLSI. 66-72 - Carl Sechen:
Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. 73-80 - Barry Whalen:
Automating the Design of Electronic Packaging (tutorial). 81 - David A. Hodges:
Opportunities in Computer Integrated Manufacturing. 82-83 - Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal:
Contest: A Concurrent Test Generator for Sequential Circuits. 84-89 - C. Thomas Glover, M. Ray Mercer:
A Method of Delay Fault Test Generation. 90-95 - Wu-Tung Cheng:
Split Circuit Model for Test Generation. 96-101 - Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder:
A Notation for Describing Multiple Views of VLSI Circuits. 102-107 - Paul J. Drongowski, Jwahar R. Bami, Ranganathan Ramaswamy, Sundar Iyengar, Tsu-Hua Wang:
A Graphical Hardware Design Language. 108-114 - Gotaro Odawara, Masahiro Tomita, Kazuhiko Hattori, Osamu Okuzawa, Toshiaki Hirata, Masayasu Ochiai:
A Human Machine Interface for Silicon Compilation. 115-120 - C. P. Ravikumar, Sarma Sastry:
Parallel Placement on Reduced Array Architecture. 121-127 - Mehdi R. Zargham:
Parallel Channel Routing. 128-133 - Erik C. Carlson, Rob A. Rutenbar:
Mask Verification on the Connection Machine. 134-140 - Andrew Rappaport:
Future Computing Environments for DA (panel). 141 - Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni:
On Path Selection in Combinational Logic Circuits. 142-147 - James J. Cherry:
Pearl: A CMOS Timing Analyzer. 148-153 - David E. Wallace, Carlo H. Séquin:
ATV: An Abstract Timing Verifier. 154-159 - Mary L. Bailey, Lawrence Snyder:
An Empirical Study of On-chip Parallelism. 160-165 - Larry Soulé, Tom Blank:
Parallel Logic Simulation on General Purpose Machines. 166-171 - David M. Lewis:
A Programmable Hardware Accelerator for Compiled Electrical Simulation. 172-177 - Walter Heyns, K. Van Nieuwenhove:
Recursive Channel Router. 178-182 - H. Cai:
Multi-Pads, Single Layer Power Net Routing in VLSI Circuits. 183-188 - Jonathan Rose:
LocusRoute: A Parallel Global Router for Standard Cells. 189-195 - Tom Blank:
Behavioral Modeling for System Design (panel). 196 - Victoria Stavridou, Howard Barringer, David A. Edwards:
Formal Specification and Verification of Hardware: A Comparative Case Study. 197-204 - Jean Christophe Madre, Jean-Paul Billon:
Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour. 205-210 - Paliath Narendran, Jonathan Stillman:
Formal Verification of the Sobel Image Processing Chip. 211-217 - Daniel K. Beece, George Deibert, Georgina Papp, Frank Villante:
The IBM Engineering Verification Engine. 218-224 - Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato:
Logic Simulation System Using Simulation Processor (SP). 225-230 - Yoshiharu Kazama, Yoshiaki Kinoshita, Motonobu Nagafuji, Hiroshi Murayama:
Algorithm for Vectorizing Logic Simulation and Evaluation of "VELVET" Performance. 231-236 - Richard Barth, Bertrand Serlet:
A Structural Representation for VLSI Design. 237-242 - Richard Barth, Bertrand Serlet, Pradeep S. Sindhu:
Parameterized Schematics. 243-249 - Richard Barth, Louis Monier, Bertrand Serlet:
Patchwork: Layout from Schematic Annotations. 250-255 - Wayne H. Wolf:
What Is a Design Automation Framework, Anyway? (panel). 256 - Gwo-Dong Chen, Tai-Ming Parng:
A Database Management System for a VLSI Design System. 257-262 - Ying-Kuei Yang:
An Enhanced Data Model for CAD/CAM Database Systems. 263-268 - David Gedye, Randy H. Katz:
Browsing in Chip Design Database. 269-274 - Hong-Tai Chou, Won Kim:
Versions and Change Notification in an Object-Oriented Database System. 275-281 - Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam:
An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. 282-287 - Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj:
Delay Modeling and Time of Bipolar Digital Circuits. 288-293 - Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar:
Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. 294-299 - Carol V. Gura, Jacob A. Abraham:
Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics. 300-305 - Jimmy Lam, Jean-Marc Delosme:
Performance of a New Annealing Schedule. 306-311 - Sivanarayana Mallela, Lov K. Grover:
Clustering Based Simulated Annealing for Standard Cell Placement. 312-317 - Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu:
Proud: A Fast Sea-of-Gates Placement Algorithm. 318-323 - Lawrence T. Pillage, Ronald A. Rohrer:
A Quadratic Metric with a Simple Solution Scheme for Initial Placement. 324-329 - Michael C. McFarland, Alice C. Parker, Raul Camposano:
Tutorial on High-Level Synthesis. 330-336 - Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn:
The System Architect's Workbench. 337-343 - Denise J. Ecklund, Fred M. Tonge:
A Context Mechanism to Control Sharing in a Design Database. 344-350 - Pieter van der Wolf, T. G. R. M. van Leuken:
Object Type Oriented Data Modeling for VLSI Data Management. 351-356 - Ing Widya, T. G. R. M. van Leuken, Pieter van der Wolf:
Concurrency Control in a VLSI Design Database. 357-362 - Agnieszka Konczykowska, M. Bon:
Automated Design Software for Switched-Capacitor IC's with Symbolic Simulator SCYMBAL. 363-368 - E. Berkcan, Manuel A. d'Abreu, W. Laughton:
Analog Compilation Based on Successive Decompositions. 369-375 - Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen:
Model Development and Verification for High Level Analog Blocks. 376-382 - David G. Boyer:
Symbolic Layout Compaction Review. 383-389 - Werner L. Schiele:
Compaction with Incremental Over-Constraint Resolution. 390-395 - David Marple, Michiel Smulders, Henk Hegen:
An Efficient Compactor for 45° Layout. 396-402 - Nels Vander Zanden, Daniel Gajski:
MILO: A Microarchitecture and Logic Optimizer. 403-408 - Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou:
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. 409-414 - Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose:
Bridge: A Versatile Behavioral Synthesis System. 415-420 - Chin-Long Wey, Tsin-Yuan Chang:
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. 421-426 - Martin Helliwell, Marek A. Perkowski:
A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms. 427-432 - Wayne H. Wolf, Kurt Keutzer, Janaki Akella:
A Kernel-Finding State Assignment Algorithm for Multi-Level Logic. 433-438 - Yoichi Shiraishi, Jun'ya Sakemi, Makoto Kutsuwada, Akira Tsukizoe, Takashi Satoh:
A High Packing Density Module Generator for CMOS Logic Cells. 439-444 - Donald G. Baltus, Jonathan Allen:
SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics. 445-452 - Fred W. Obermeier, Randy H. Katz:
An Electrical Optimizer that Considers Physical Layout. 453-459 - Don Stark, Mark Horowitz:
Analyzing CMOS Power Supply Networks Using Ariel. 460-464 - Volker Henkel, Ulrich Golze:
RISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification. 465-470 - Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo:
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. 471-475 - Randal E. Bryant:
CAD Tool Needs for System Designers. 476 - Gaetano Borriello, Ewald Detjens:
High-Level Synthesis: Current Status and Future Directions. 477-482 - Giovanni De Micheli, David C. Ku:
HERCULES - a System for High-Level Synthesis. 483-488 - Raul Camposano:
Design Process Model in the Yorktown Silicon Compiler. 489-494 - Derek L. Beatty, Randal E. Bryant:
Fast Incremental Circuit Analysis Using Extracted Hierarchy. 495-500 - Kiyoung Choi, Sun Young Hwang, Tom Blank:
Incremental-in-time Algorithm for Digital Simulation. 501-505 - Dan Adler:
A Dynamically-Directed Switch Model for MOS Logic Simulation. 506-511 - Makoto Takashima, Atsuhiko Ikeuchi, Shoichi Kojima, Toshikazu Tanaka, Tamaki Saitou, Jun-ichi Sakata:
A Circuit Comparison System with Rule-Based Functional Isomorphism Checking. 512-516 - Michael Boehner:
LOGEX - an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology. 517-522 - Alexander C. Papaspyrdis:
A Prolog-Based Connectivity Verification Tool. 523-527 - Alfred E. Dunlop:
Will Cell Generation Displace Standard Cells? 528 - Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig:
CORAL II: Linking Behavior and Structure in an IC Design System. 529-535 - Barry M. Pangre:
Splicer: A Heuristic Approach to Connectivity Binding. 536-541 - Rajiv Jain, Alice C. Parker, Nohbyung Park:
Module Selection for Pipelined Synthesis. 542-547 - Rami R. Razouk:
The Use of Petri Nets for Modeling Pipelined Processors. 548-553 - Yue-Sun Kuo, T. C. Chern, Wei-Kuan Shih:
Fast Algorithm for Optimal Layer Assignment. 554-559 - H. Cai:
Connectivity Biased Channel Construction and Ordering for Building-Block Layout. 560-565 - Xianji Yao, Masaaki Yamada, C. L. Liu:
A New Approach to the Pin Assignment Problem. 566-572 - Xiao-Ming Xiong, Ernest S. Kuh:
The Constrained Via Minimization Problem for PCB and VLSI Design. 573-578 - Chien-Hung Chao, F. Gail Gray:
Micro-operation Perturbations in Chip Level Fault Modeling. 579-582 - Fredrick J. Hill, Eltayeb Abuelyamen, Wei-Kang Huang, Guo-Qiang Shen:
A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits. 583-586 - Mehmet A. Cirit:
Switch Level Random Pattern Testability Analysis. 587-590 - Weiwei Mao, Michael D. Ciletti:
Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation. 591-596 - Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler:
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. 597-600 - Dov Harel, Balakrishnan Krishnamurthy:
A Graph Compaction Approach to Fault Simulation. 601-604 - Chen-Shang Lin, Hong-Fa Ho:
Automatic Functional Test Program Generation for Microprocessors. 605-608 - Sy-Yen Kuo, W. Kent Fuchs:
Spare Allocation and Reconfiguration in Large Area VLSI. 609-612 - Steve Meyer:
A Data Structure for Circuit Net Lists. 613-616 - Michel Heydemann, Alain Plaignaud, Daniel Dure:
The Architecture of a Highly Integrated Simulation System. 617-621 - William C. Diss:
Circuit Compilers don't have to be Slow. 622-627 - Tai A. Ly, Emil F. Girczyc:
Constraint Propagation in an Object-Oriented IC Design Environment. 628-633 - Sheldon S. L. Chang:
Design Automation for the Component Parts Industry. 634-637 - Marwan A. Jabri:
Automatic Building of Graphs for Rectangular Dualisation. 638-641 - Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa:
Automatic Layout Procedures for Serial Routing Devices. 642-645 - Richard I. Hartley, Peter F. Corbett:
A Digit-Serial Silicon Compiler. 646-649 - Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin:
DECOMPOSER: A Synthesizer for Systolic Systems. 650-653 - Thomas Bergstraesser, Jürgen Gessner, Karlheinz Hafner, Stefan Wallstab:
SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture. 654-657 - Atreyi Chakraverti, Moon-Jung Chung:
Routing Algorithm for Gate Array Macro Cells. 658-662 - Jingsheng Cong, D. F. Wong
:
How to Obtain More Compactable Channel Routing Solutions. 663-666 - R. Eric Lunow:
A Channelless, Multilayer Router. 667-671 - Michael H. Arnold, Walter S. Scott:
An Interactive Maze Router with Hints. 672-676 - Chung-Kuan Cheng, David N. Deutsch:
Improved Channel Routing by Via Minimization and Shifting. 677-680 - Inderpal S. Bhandari, Mark Hirsch, Daniel P. Siewiorek:
The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-cut Placement. 681-685 - Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers:
Fault Simulation in a Distributed Environment. 686-691 - Silvano Gai, Pier Luca Montessoro, Fabio Somenzi:
The Performance of the Concurrent Fault Simulation Algorithms in MOZART. 692-697 - Akira Motohara, Motohide Murakami, Miki Urano, Yasuo Masuda, Masahide Sugano:
An Approach to Fast Hierarchical Fault Simulation. 698-703 - Jacob Savir:
Why Partial Design Verification Works Better Than It Should. 704-707 - Richard H. Lathrop, Robert J. Hall, Gavan Duffy, K. Mark Alexander, Robert S. Kirk:
Advances in Functional Abstraction from Structure. 708-711 - Craig Hansen:
Hardware Logic Simulation by Compilation. 712-716 - Yoshio Takamine, Shunsuke Miyamoto, Shigeo Nagashima, Masayuki Miyoshi, Shun Kawabe:
Clock Event Suppression Algorithm of VELVET and Its Application to S-820 Development. 716-719 - H. C. Yen, Subbarao Ghanta, David Hung-Chang Du:
A Path Selection Algorithm for Timing Analysis. 720-723 - Steven K. Sherman:
Algorithms for Timing Requirement Analysis and Generation. 724-727
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