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ORCIDDATE 2020: Grenoble, France
- 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020. IEEE 2020, ISBN 978-3-9819263-4-7
- Koen Bertels, Aritra Sarkar
, Thomas Hubregtsen, M. Serrao, Abid A. Mouedenne, Amitabh Yadav, A. M. Krol, Imran Ashraf:
Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators. 1-6 - Brice Colombier, Nathalie Bochard, Florent Bernard, Lilian Bossuet:
Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator. 1-6 - Rui Wang, Georgios N. Selimis, Roel Maes, Sven Goossens:
Long-term Continuous Assessment of SRAM PUF and Source of Random Numbers. 7-12 - Amin Rezaei, Yuanqi Shen, Hai Zhou:
Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation. 13-18 - Bin Lin, Jinchao Chen, Fei Xie:
Selective Concolic Testing for Hardware Trojan Detection in Behavioral SystemC Designs. 19-24 - Chris Nigh, Alex Orailoglu:
Test Pattern Superposition to Detect Hardware Trojans. 25-30 - Sandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks. 31-36 - Lennart Bamberg, Alberto García Ortiz, Lingjun Zhu, Sai Pentapati, Da Eun Shim, Sung Kyu Lim:
Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. 37-42 - Abdallah M. Felfel, Kamalika Datta, Arko Dutt, Hasita Veluri, Ahmed Zaky, Aaron Voon-Yew Thean, Mohamed M. Sabry Aly:
Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM. 43-48 - Ting-Jung Chang, Zhuozhi Yao, Barry P. Rand, David Wentzlaff:
Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit. 49-54 - Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar:
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. 55-60 - Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louërat, Amine Rhouni, Hassan Aboushady, Haralampos-G. D. Stratigopoulos:
Securing Programmable Analog ICs Against Piracy. 61-66 - Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. 67-72 - Byungmin Ahn, Taewhan Kim:
Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks. 73-78 - Kwangbae Lee, Hoseung Kim, Hayun Lee, Dongkun Shin:
Flexible Group-Level Pruning of Deep Neural Networks for On-Device Machine Learning. 79-84 - Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan:
Sparsity-Aware Caches to Accelerate Deep Neural Networks. 85-90 - Song Jin, Songwei Pei, Yu Wang:
On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target Sparsifying. 91-96 - Liang Pang, Mengyun Yao, Yifan Chai:
An Efficient SRAM yield Analysis Using Scaled-Sigma Adaptive Importance Sampling. 97-102 - Michael Hefenbrock, Dennis D. Weller, Michael Beigl, Mehdi Baradaran Tahoori:
Fast and Accurate High-Sigma Failure Rate Estimation through Extended Bayesian Optimized Importance Sampling. 103-108 - Min Ye, Qiao Li, Jianqiang Nie, Tei-Wei Kuo, Chun Jason Xue:
Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory. 109-114 - Yeseong Kim, Mohsen Imani, Niema Moshiri, Tajana Rosing:
GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional Computing. 115-120 - Sidharth Maheshwari, Rishad A. Shafik, Ian Wilson, Alex Yakovlev, Amit Acharyya:
REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics. 121-126 - Dayane Reis, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu:
A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications. 127-132 - Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli:
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). 133-138 - Xifan Tang, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore, Pierre-Emmanuel Gaillardon:
A RRAM-based FPGA for Energy-efficient Edge Computing. 144- - Zi Wang, Jianqi Chen, Benjamin Carrión Schäfer:
Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization. 145-150 - Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin:
Prospector: Synthesizing Efficient Accelerators via Statistical Learning. 151-156 - Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim:
Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. 157-162 - Markus Planner, Sabine Ott, Sebastian Albrecht, Jintin Tran, Christopher Mandla, Jan-Christoph Tenzer, Thomas Schanz, Samuel Pliego, Denis Tcherniak, Manfred Steller, Harald Jeszensky, Roland Ottensamer, Konrad R. Skup, Chris Thomas, Julian Thornhill:
ESA Athena WFI Onboard Electronics - Distributed Control and Data Processing. 163-168 - Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber:
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. 169-174 - Christos Kotselidis, Sotiris Diamantopoulos, Orestis Akrivopoulos, Viktor Rosenfeld, Katerina Doka, Hazeef Mohammed, Georgios Mylonas, Vassilis Spitadakis, Will Morgan:
Efficient Compilation and Execution of JVM-Based Data Processing Frameworks on Heterogeneous Co-Processors. 175-179 - Nagadastagiri Challapalle, Sahithi Rampalli, Makesh Chandran, Gurpreet S. Kalsi, Sreenivas Subramoney, John Sampson, Vijaykrishnan Narayanan:
PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks. 180-185 - Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini:
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions. 186-191 - Xingbin Wang, Boyan Zhao, Rui Hou, Dan Meng:
SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network Structure. 192-197 - Renwei Li, Junning Wu, Meng Liu, Zuding Chen, Shengang Zhou, Shanggong Feng:
HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System. 198-203 - Jinghao Sun, Yaoyao Chi, Tianfei Xu, Lei Cao, Nan Guan, Zhishan Guo, Wang Yi:
On the Volume Calculation for Conditional DAG Tasks: Hardness and Algorithms*. 204-209 - Simon Reder, Jürgen Becker:
WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers. 210-215 - Antoine Bertout, Joël Goossens, Emmanuel Grolleau, Xavier Poczekajlo:
Template schedule construction for global real-time scheduling on unrelated multiprocessor platforms. 216-221 - Kacper Wardega, Wenchao Li:
Application-Aware Scheduling of Networked Applications over the Low-Power Wireless Bus. 222-227 - Biresh Kumar Joardar, Nitthilan Kannappan Jayakodi, Janardhan Rao Doppa, Hai Li, Partha Pratim Pande, Krishnendu Chakrabarty:
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation. 228-233 - Ling Wang, Yadong Wang, Xiaohang Wang:
An Approximate Multiplane Network-on-Chip. 234-239 - Bo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh:
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip. 240-245 - Michael Hersche, Philipp Rupp, Luca Benini, Abbas Rahimi:
Compressing Subject-specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional Space. 246-251 - Konstantinos Malavazos, Maria Papadogiorgaki, Pavlos Malakonakis, Ioannis Papaefstathiou:
A novel FPGA-based system for Tumor Growth Prediction. 252-257 - Silvio Zanoli, Tomás Teijeiro, Fabio Montagna, David Atienza:
An Event-Based System for Low-Power ECG QRS Complex Detection. 258-263 - Giovanni Mezzina, Daniela De Venuto:
Semi-Autonomous Personal Care Robots Interface driven by EEG Signals Digitization. 264-269 - Nimisha Limaye, Ozgur Sinanoglu:
DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. 270-273 - Ismail Cevik, Levent Aksoy, Mustafa Altun:
CMOS Implementation of Switching Lattices. 274-277 - Soheil Nazar Shahsavani, Bo Zhang, Massoud Pedram:
A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits. 278-281 - Antonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar, Haralampos-G. D. Stratigopoulos:
Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP. 282-285 - Sai Govinda Rao Nimmalapudi, Georgios Volanis, Yichuan Lu, Angelos Antonopoulos, Andrew Marshall, Yiorgos Makris:
Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs. 286-289 - Koutaro Hachiya, Atsushi Kurokawa:
Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation. 290-293 - Filip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU. 294-297 - Valentin Gherman, Samuel Evain, Bastien Giraud:
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. 298-301 - Meng Zhang, Fei Wu, Qin Yu, Weihua Liu, Lanlan Cui, Yahui Zhao, Changsheng Xie:
BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory. 302-305 - Kang Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg:
Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots. 306-309 - Milind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia:
SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware. 310-313 - Ipsita Koley, Saurav Kumar Ghosh, Soumyajit Dey, Debdeep Mukhopadhyay, Amogh Kashyap K. N., Sachin Kumar Singh, Lavanya Lokesh, Jithin Nalu Purakkal, Nishant Sinha:
Formal Synthesis of Monitoring and Detection Systems for Secure CPS Implementations. 314-317 - Bahar Asgari, Ramyad Hadidi, Hyesoon Kim:
ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory. 318-321 - Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst:
Acceleration of probabilistic reasoning through custom processor architecture. 322-325 - Shayan Tabatabaei Nikkhah, Marc Geilen, Dip Goswami, Kees Goossens:
A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources. 326-329 - Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maiza:
Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems. 330-333 - Subodha Charles, Megan Logan, Prabhat Mishra:
Lightweight Anonymous Routing in NoC based SoCs. 334-337 - Markus Reichmuth, Simone Schürle, Michele Magno:
A Non-invasive Wearable Bioimpedance System to Wirelessly Monitor Bladder Filling. 338-341 - Michele Magno, Xiaying Wang, Manuel Eggimann, Lukas Cavigelli, Luca Benini:
InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting. 342-345 - Ahmet Can Mert, Emre Karabulut, Erdinç Öztürk, Erkay Savas, Michela Becchi, Aydin Aysu:
A Flexible and Scalable NTT Hardware : Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography. 346-351 - Jeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung-Hee Cho, Jaeyong Chung, Joon-Sung Yang:
Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture. 352-357 - Zhiqian Chen, Gaurav Kolhe, Setareh Rafatirad, Chang-Tien Lu, Sai Manoj P. D., Houman Homayoun, Liang Zhao:
Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning. 358-363 - Johannes Feldmann, Kira Kraft, Lukas Steiner, Norbert Wehn, Matthias Jung:
Fast and Accurate DRAM Simulation: Can we Further Accelerate it? 364-369 - Breytner Fernández-Mesa, Liliana Andrade, Frédéric Pétrot:
Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC. 370-375 - Fei Gao, Frédéric Mallet, Min Zhang, Mingsong Chen:
Modeling and Verifying Uncertainty-Aware Timing Behaviors using Parametric Logical Time Constraint. 376-381 - Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, Csaba Andras Moritz:
Nano-Crossbar based Computing: Lessons Learned and Future Directions. 382-387 - Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka:
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. 388-393 - Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat:
A Universal Spintronic Technology based on Multifunctional Standardized Stack. 394-399 - Zihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Zhengmao Lu, Evelyn Wang, Sherief Reda, Ayse K. Coskun:
A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies. 400-405 - Mengquan Li, Jun Zhou, Weichen Liu:
Lightweight Thermal Monitoring in Optical Networks-on-Chip via Router Reuse. 406-411 - Zhiqiang Zhao, Zhuo Feng:
A Spectral Approach to Scalable Vectorless Thermal Integrity Verification. 412-417 - Arman Iranfar, Federico Terraneo, Gabor Csordas, Marina Zapater, William Fornaciari, David Atienza:
Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning. 418-423 - Linwei Niu, Dakai Zhu:
Reliable and Energy-Aware Fixed-Priority (m, k)-Deadlines Enforcement with Standby-Sparing. 424-429 - Monowar Hasan, Sibin Mohan, Rodolfo Pellizzoni, Rakesh B. Bobba:
Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems. 430-435 - Jiankang Ren, Xin He, Junlong Zhou, Hongwei Ge, Guowei Wu, Guozhen Tan:
Efficient Latency Bound Analysis for Data Chains of Real-Time Tasks in Multiprocessor Systems. 436-441 - Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar:
Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems. 442-447 - Rajit Karmakar, Santanu Chattopadhyay:
A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access. 448-453 - Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi:
Effect of Aging on PUF Modeling Attacks based on Power Side-Channel Observations. 454-459 - Sebastian P. Bayerl, Tommaso Frassetto, Patrick Jauernig, Korbinian Riedhammer, Ahmad-Reza Sadeghi, Thomas Schneider, Emmanuel Stapf, Christian Weinert:
Offline Model Guard: Secure and Private ML on Mobile Devices. 460-465 - Minhui Zou, Zhenhua Zhu, Yi Cai, Junlong Zhou, Chengliang Wang, Yu Wang:
Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections. 466-471 - Loai Danial, V. Gupta, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky:
Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing. 472-477 - Naveen Kumar Katam, Bo Zhang, Massoud Pedram:
Ground Plane Partitioning for Current Recycling of Superconducting Circuits. 478-483 - Asif Mirza, Febin Sunny, Sudeep Pasricha, Mahdi Nikdast:
Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity. 484-489 - Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic:
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs. 490-495 - Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. 496-501 - Zhiyuan Zhou, Syrine Belakaria, Aryan Deshwal, Wookpyo Hong, Janardhan Rao Doppa, Partha Pratim Pande, Deukhyoun Heo:
Design of Multi-Output Switched-Capacitor Voltage Regulator via Machine Learning. 502-507 - Johann Knechtel, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei, Yaacov Belenky, Itamar Levi, Tim Güneysu, Patrick Schaumont, Ilia Polian:
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. 508-513 - Fatemeh Ganji, Sarah Amir, Shahin Tajik, Domenic Forte, Jean-Pierre Seifert:
Pitfalls in Machine Learning-based Adversary Modeling for Hardware Systems. 514-519 - Ran Canetti, Marten van Dijk, Hoda Maleki, Ulrich Rührmair, Patrick Schaumont:
Using Universal Composition to Design and Analyze Secure Complex Hardware Systems. 520-525 - Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz:
Gap-free Processor Verification by S2QED and Property Generation. 526-531 - Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. 532-537 - Nícolas Pfeifer, Bruno V. Zimpel, Gabriel A. G. Andrade, Luiz C. V. dos Santos:
A Reinforcement Learning Approach to Directed Test Generation for Shared Memory Verification. 538-543 - Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler:
Towards Formal Verification of Optimized and Industrial Multipliers. 544-549 - Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri:
Is Register Transfer Level Locking Secure? 550-555 - Valentina Richthammer, Marcel Rieß, Julian Bestler, Frank Slomka, Michael Glaß:
Design Space Exploration for Model-based Communication Systems. 556-561 - Nadir Amin Carreon, Allison Gilbreath, Roman Lysecky:
Statistical Time-based Intrusion Detection in Embedded Systems. 562-567 - Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli:
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks. 568-573 - Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel:
Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs. 574-579 - Anna Bernasconi, Valentina Ciriani, Jordi Cortadella, Tiziano Villa:
Computing the full quotient in bi-decomposition by approximation. 580-585 - Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang:
MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. 586-591 - Timothy J. Baker, John P. Hayes:
The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing. 592-597 - Kuncai Zhong, Weikang Qian:
Accuracy Analysis for Stochastic Circuits with D Flip-Flop Insertion. 598-603 - Siting Liu, Jie Han:
Dynamic Stochastic Computing for Digital Signal Processing Applications. 604-609 - Michael X. Lyons, Kris Gaj:
Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography. 610-613 - Amir Alipour, Athanasios Papadimitriou, Vincent Beroulle, Ehsan Aerabi, David Hély:
On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure. 614-617 - Vladimir Herdt, Daniel Große, Rolf Drechsler:
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*. 618-621 - Shiyu Zhang, Juan Zhai, Lei Bu, Mingsong Chen, Linzhang Wang, Xuandong Li:
Automated Generation of LTL Specifications For Smart Home IoT Using Natural Language. 622-625 - Hao Feng, Yuhui Deng, Yi Zhou:
A Heat-Recirculation-Aware VM Placement Strategy for Data Centers. 626-629 - Sami Salamin, Martin Rapp, Hussam Amrouch, Andreas Gerstlauer, Jörg Henkel:
Energy Optimization in NCFET-based Processors. 630-633 - Soulimane Kamni, Yassine Ouhammou, Antoine Bertout, Emmanuel Grolleau:
Towards a Model-based Multi-Objective Optimization Approach For Safety-Critical Real-Time Systems. 634-637 - Shengqi Yu, Ahmed Soltan, Rishad A. Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo, Alex Yakovlev:
Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture. 638-641