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ORCID19th DDECS 2016: Kosice, Slovakia
- 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, Slovakia, April 20-22, 2016. IEEE 2016, ISBN 978-1-5090-2467-4
Session 1A: Soft Errors and Reliability
- Gökçe Aydos
, Görschwin Fey:
Exploiting error detection latency for parity-based soft error detection. 3-8 - Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
System-level reliability evaluation through cache-aware software-based fault injection. 9-14 - Aitzan Sari, Mihalis Psarakis:
A fault injection platform for the analysis of soft error effects in FPGA soft processors. 15-20 - Jaroslav Borecký, Martin Kohlík, Hana Kubátová:
Parity Waterfall method. 21-26
Session 1B: Analog Design
- Matej Rakus, Viera Stopjaková, Daniel Arbet:
Comparison of gate-driven and bulk-driven current mirror topologies. 27-30 - Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang:
A chaotically injected timing technique for ring-based oscillators. 31-34 - Dinka Milovancev, Paul Brandl, Nemanja Vokic, Bernhard Goll, Kerstin Schneider-Hornstein, Horst Zimmermann:
Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration. 35-39 - Daniel Arbet, Martin Kovác, Lukás Nagy, Viera Stopjaková, Juraj Brenkus:
Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology. 40-45
Session 2A: Digital Design
- Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-objective BDD optimization for RRAM based circuit design. 46-51 - Sergiu Nimara, Oana Boncalo, Alexandru Amaricai, Mircea Popa:
FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization. 52-55 - Thomas Polzer, Andreas Steininger:
A general approach for comparing metastable behavior of digital CMOS gates. 56-61 - Klaus Tittelbach-Helmrich, Zoran Stamenkovic:
Hardware implementation of a medium access control layer for industrial wireless LAN. 62-67
Session 2B: Mixed-signal Design & Test
- Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor:
Comparative BTI analysis for various sense amplifier designs. 68-73 - Juraj Brenkus, Viera Stopjaková, Lukás Nagy, Daniel Arbet:
Impedance calculation based method for AC fault analysis of mixed-signal circuits. 74-79 - Engin Afacan, Günhan Dündar:
A mixed domain sizing approach for RF circuit synthesis. 80-83 - Muhammad Waqas Chaudhary, Andy Heinig:
Co-design of CML IO and Interposer channel for low area and power signaling. 84-89
Embedded Tutorial
- Lukás Sekanina:
Introduction to approximate computing: Embedded tutorial. 90-95
Session 3A: Medical Applications
- Dmitry Osipov, Steffen Paul:
8 Channel neural stimulation ASIC for epidural visual cortex stimulation with on board 90 ppm/°C current reference. 96-101 - Krzysztof Siwiec, Krzysztof Marcinek, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus, Witold A. Pleskacz:
BioSoC: Highly integrated System-on-Chip for health monitoring. 102-107 - Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz:
Precision human body temperature measurement based on thermistor sensor. 108-112
Session 3B: Microprocessor Test
- Christian Gleichner, Heinrich Theodor Vierhaus:
Test of automotive embedded processors with high diagnostic resolution. 113-118 - Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective approach for functional test programs compaction. 119-124 - Boyang Du, Ernesto Sánchez, Matteo Sonza Reorda, Julio Pérez Acle, Anton Tsertov:
FPGA-controlled PCBA power-on self-test using processor's debug features. 125-130
Session 4A: Design for Testability
- Ondrej Novák, Jiri Jenícek, Martin Rozkovec:
Sequential test decompressors with fast variable wide spreading. 132-137 - Stefan Kristofík, Marcel Baláz:
Built-in self-repair architecture generator for digital cores. 138-143 - Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar:
High-level modeling and testing of multiple control faults in digital systems. 144-149
Session 5A: Power-aware Design
- Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A hybrid power modeling approach to enhance high-level power models. 151-156 - Dominik Macko, Katarína Jelemenská, Pavel Cicák:
Early-stage verification of power-management specification in low-power systems design. 157-162 - Erik Ramsgaard Wognsen, René Rydhof Hansen, Kim Guldstrand Larsen, Peter Koch:
Energy-aware scheduling of FIR filter structures using a timed automata model. 163-168
Session 6A: Industrial Applications
- Arkadiusz Koczor, Lukasz Matoga, Piotr Penkala, Adam Pawlak:
Verification approach based on emulation technology. 169-174 - Oliver Schrape, Arkadiusz Koczor, Piotr Penkala, Vladimir Petrovic, Milos Krstic:
Implementation of DBFN processor for Synthetic Aperture Radar application. 175-179 - Aleksandar Simevski, Klaus Schleisiek, Vladimir Petrovic, Norbert Beller, Patryk Skoncej, Günter Schoof, Milos Krstic:
Implementation of a real time unit for satellite applications. 180-185
Session 6A: Industrial Applications
- Alexei Evgenievich Titov, Nikolay Nikolaevich Prokopenko, Ilya Viktorovich Pakhomov:
The design features of low-temperature radiation-hardened instrumentation amplifiers and sensor interfaces. 186-189 - Róbert Tamási, Miroslav Siebert, Elena Gramatová, Petr Fiser:
A new method for path criticality calculation. 190-193 - Delong Shang, Yuqing Xu, Kaiyuan Gao, Fei Xia, Alex Yakovlev:
Low power voltage sensing through capacitance to digital conversion. 194-199 - Artemios G. Voyiatzis, Kyriakos G. Stefanidis, Paris Kitsos:
Efficient triggering of Trojan hardware logic. 200-205 - Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng:
Gm-C filter with automatic calibration scheme. 206-209 - Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser:
A new user-friendly ATPG platform for digital circuits. 210-213 - Tomas Vanat, Filip Krizek, Jozef Ferencei, Hana Kubátová:
Comparing proton and neutron induced SEU cross section in FPGA. 214-217 - Igor Butryn, Krzysztof Siwiec, Jakub Kopanski, Witold A. Pleskacz:
Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology. 218-221 - Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng:
Low-voltage indoor energy harvesting using photovoltaic cell. 223-226 - Ondrej Kachman, Marcel Baláz:
Optimized differencing algorithm for firmware updates of low-power devices. 227-230 - Michael S. Saleab, Mohamed A. Abd El-Ghany, Ramez M. Toma, Klaus Hofmann:
Real-time sleep detection and warning system to ensure driver's safety based on EEG. 231-236 - Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das:
A rule-based approach for minimizing power dissipation of digital circuits. 237-242 - Michal Sovcik, Michal Matuska, Daniel Arbet, Viera Stopjaková:
CMOS variable-gain amplifier for low-frequency applications. 243-246
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