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ORCID5th FPL 1995: Oxford, UK
- Will Moore, Wayne Luk:
Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings. Lecture Notes in Computer Science 975, Springer 1995, ISBN 3-540-60294-1
Architectures
- Tony Stansfield, Ian Page:
The Design of a New FPGA Architecture. 1-14 - John Turner, Richard Cliff, W. Leong, Cameron McClintock, Ninh Ngo, Khai Nguyen, Chiakang Sung, Bonnie Wang, J. Watson:
Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. 15-20 - Rob Payne:
Self-Timed FPGA Systems. 21-35 - Steven Churcher, Tom Kean, Bill Wilkie:
XC6200 FastmapTM Processor Interface. 36-43 - Greg Snider, Philip Kuekes, W. Bruce Culbertson, Richard J. Carter, Arnold S. Berger, Rick Amerson:
The Teramac Configurable Computer Engine. 44-53 - Toshiaki Miyazaki, Kazuhisa Yamada, Akihiro Tsutsui, Hiroshi Nakada, Naohisa Ohta:
Telecommunication-Oriented FPGA and Dedicated CAD System. 54-67
Platforms
- Paul A. Dunn:
A Configurable Logic Processor for Machine Vision. 68-77 - Peter Schulz:
Extending DSP-Boards with FPGA-Based Structures of Interconnection. 78-85 - Ramana V. Rachakonda, Peter M. Athanas, A. Lynn Abbott:
High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform. 86-93 - Christophe Beaumont:
Using FPGAs as Control Support in MIMD Executions. 94-103 - Fabio G. Guerrero
, James M. Noras:
Customised Hardware Based on the REDOC III Algorithm for High-Performance Date Ciphering. 104-110 - Adrian Lawrence, Andrew Kay, Wayne Luk, Toshio Nomura, Ian Page:
Using Reconfigurable Hardware to Speed up Product Development and Performance. 111-118 - Steve Casselman, Michael Thornburg, John Schewel:
Creation of Hardware Objects in a Reconfigurable Computer. 119-128 - Laurence E. Turner, Peter J. W. Graumann:
Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs. 129-138
Tools
- A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. 139-148 - Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses:
Some Notes on Power Management on FPGA-Based Systems. 149-157 - Keith R. Dimond:
An Automatic Technique for Realising User Interaction Processing in PLD Based Systems. 158-167 - Carol A. Fields:
The Proper Use of Hierarchy in HDL-Based High Density FPGA Design. 168-177 - William P. Marnane, C. N. Jordan, F. J. O'Reilly:
Compiling Regular Arrays onto FPGAs. 178-187 - Shaori Guo, Wayne Luk:
Compiling Ruby into FPGAs. 188-197 - David J. Greaves:
The CSYN Verilog Compiler and Other Tools. 198-207 - Michael Gschwind, Valentina Salapura:
A VHDL Design Methodology for FPGAs. 208-217 - Maziar Khosravipour, Herbert Grünbacher:
VHDL-Based Rapid Hardware Prototyping Using FPGA Technology. 218-226 - Markus Weinhardt:
Integer Programming for Partitioning in Software Oriented Codesign. 227-234 - Kristin Ahrens:
Test Standard Serves Dual Role as On-Board Programming Solution. 235-240 - U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner:
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. 241-250
Arithmetic and Signal Processing
- Tudor Jebelean:
FPGA Implementation of a Rational Adder. 251-260 - André Klindworth:
FPLD Implementation of Computation over Finite Fields GF(2m) with Applications to Error Control Coding. 261-271 - Gopal Panneerselvam, Peter J. W. Graumann, Laurence E. Turner:
Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs. 272-281 - Nabeel Shirazi, Peter M. Athanas, A. Lynn Abbott:
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine. 282-292 - Russell J. Petersen, Brad L. Hutchings:
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing. 293-302 - Peter Lee:
An FPGA Prototype for a Multiplierless FIR Filter Built Using the Logarithmic Number System. 303-310 - Laurence E. Turner, Peter J. W. Graumann, S. G. Gibb:
BIT-Serial FIR Filters with CSD Coefficients for FPGAs. 311-320
Embedded Systems and Other Applications
- M. Atia, J. Bowles, David W. Clarke, M. P. Henry, Ian Page, J. Randall, Janice C.-Y. Yang:
A Self-Validating Temperature Sensor Implemented in FPGAs. 321-330 - Alan S. Wenban, Geoffrey Brown, John O'Leary:
Developing Interface Libraries for Reconfigurable Data Acquisition Boards. 331-340 - Hans-Jürgen Herpel, Ulrike Ober, Manfred Glesner:
Prototype Generation of Application-Specific Embedded Controllers for Microsystems. 341-351 - Paul S. Graham, Brent E. Nelson:
A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2. 352-361 - Massimiliano Corba, Zoran Ninkov:
Modular Architecture for Real-Time Astronomical Image Processing with FPGAs. 362-369 - D. R. Woodward, Ian Page, D. C. Levy, R. G. Harley:
A Programmable I/O System for Real-Time AC Drive Control Applications. 370-379 - Rajani Cuddapah, Massimiliano Corba:
Reconfigurable Logic for Fault-Tolerance. 380-388 - Steve Guccione, Mario J. Gonzalez:
Supercomputing with Reconfigurable Architectures. 389-398
Reconfigurable Designs and Models
- Maya B. Gokhale, Aaron Marks:
Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays. 399-408 - Patrick Lysaght, Hugh Dick, Gordon Charles McGregor, David McConnell, Jon Stockwood:
Prototyping Environment for Dynamically Reconfigurable Logic. 409-418 - Brad L. Hutchings, Michael J. Wirthlin:
Implementation Approaches for Reconfigurable Logic Applications. 419-428 - Gordon J. Brebner, John Gray:
Use of Reconfigurability in Variable-Length Code Detection at Video Rates. 429-438 - Steve Guccione, Mario J. Gonzalez:
Classification and Performance of Reconfigurable Architectures. 439-448
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