default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID37th Hot Chips Symposium 2025: Stanford, CA, USA
- IEEE Hot Chips 37 Symposium, HCS 2025, Stanford, CA, USA, August 24-26, 2025. IEEE 2025, ISBN 979-8-3315-0300-0
- Mohan Kalkunte, Asad Khamisy:
ENABLING AI Infrastructure : Tomahawk Ultra - Ultra Low Latency, High Bandwidth Ethernet Switch for HPC & AI/ML applications. 1-22 - Sudeep Bhoja:
CORSAIR:An In-Memory Computing ChipletArchitecture for Inference-Time Compute Acceleration. 1-37 - Bryan Kelly:
Azure Secure Hardware Architecture : A Robust Security Foundation for Cloud Workloads. 1-23 - Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseo Kim, Gwangtae Park, Hoi-Jun Yoo:
EdgeDiff: Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI Motivation. 1 - Wooyoung Jo, Seongyon Hong, Jiwon Choi, Beomseok Kwon, Haoyang Sang, Dongseok Im, Sangyeob Kim, Sangjin Kim, Chaeyun Jeong, Yujin Moon, Hoi-Jun Yoo:
BROCA: A Low-power and Low-latency Conversational Agent RISC-V System-on-Chip for Voice-interactive Mobile Devices. 1 - Luchang Lei, Yu Duan, Cheng Peng, Yongqing Zhu, Gangfeng Du, Zhenyu Guan, Huazhong Yang, Yongpan Liu, Zhen Gu, Song Bian, Hongyang Jia:
Presto: A Unified RISC-V-Compatible SoC for Multi-Scheme FHE Acceleration over Module Lattice. 1-40 - Marc Blackstein:
RTX 5090: Designed for the Age of Neural Rendering. 1-20 - Andy Pomianowski, Laks Pappu:
AMD RDNA 4 Radeon 9000 Series GPU. 1-23 - Pat Fleming, Chihjen Chang, Derek Collier, Anjali Singhai, Stephen Doyle, Eliel Louzoun, David Lee, Vetrivel Ayyavu, Sarig Livne, Robert Hathaway, Tony Hurson, Jackson Ellis, Tamar Bar-Kanarik, Jonathan Kenny, Cristine Dumitrescu, Yaron Wolberger:
Intel® IPU E2200: Second Generation Infrastructure Processing Unit (IPU). 1-16 - Phil Winterbottom:
Photonic Interconnect for Accelerated Computing Celestial AI Photonic Fabric Module - The world's first SoC with in-die Optical IO. 1-13 - Vladimir Stojanovic:
A UCIe Optical I/O Retimer Chiplet for AI Scale-up. 1-22 - Don Soltis, Stephen Robinson:
Clearwater Forest the Next Generation Intel® Xeon® Processor with Efficiency Cores. 1-15 - Atsuyoshi Koike:
Up and Running with Rapidus : How Japan and Cutting-Edge Technologies are Transforming Semiconductor Manufacturing. 1-49 - Ohad Meitav, Jay Tsao:
Specialized IC for World-Lock Rendering in Augmented and Mixed Reality Devices. 1-18 - Norman P. Jouppi, Sridhar Lakshmanamurthy:
Ironwood: Delivering Best in Class perf, perf/TCO and perf/Watt for Reasoning Model Training and Serving. 1-26 - Noam Shazeer:
Hot ChipsKeynote. 1-45 - Mark Kuemerle:
Memory: Almost The Only Thing That Matters : A revolution in memory architecture for the data center. 1-30 - Sangyeob Kim, Jungwan Lee, Byeongju Kim, Hoi-Jun Yoo:
A 4.69mW LLM Processor with Binary/Ternary Weights for Billion-Parameter Llama Model. 1-18 - Benton H. Calhoun, David D. Wentzloff, Kuo-Ken Huang, Kyle Craig:
EveractiveSelf-Powered SoC with Energy Harvesting, Wakeup Receiver, and Energy-Aware Subsystem. 1-31 - Michael Steffen, Michael Floyd:
4th Gen AMD CDNATM Generative AI Architecture Powering AMD Instinct M350 Series GPUs and Platforms. 1-37 - Seunghyun Park, Daejin Park:
Bit-Separable Transformer Accelerator Leveraging Output Activation Sparsity for Efficient DRAM Access. 1-9 - Chang Eun Song, Weihong Xu, Keming Fan, Soumil Jain, Gopabandhu Hota, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Gert Cauwenberghs, Tajana Rosing, Mingu Kang:
Clo-HDnn: Continual On-Device Learning Accelerator with Hyperdimensional Computing via Progressive Search. 1-25 - Gilad Shainer:
Co-Packaged Silicon Photonics Switches for Gigawatt AI Factories. 1-24 - William Starke:
IBM's Power11 Processor. 1-29 - Donghyeon Han, Anantha P. Chandrakasan:
MEGA.mini: A NPU with Novel Heterogeneous AI Processing Architecture Balancing Efficiency, Performance, and Intelligence for the Era of Generative AI. 1 - Philippe Sauter, Thomas Benz, Paul Scheffler, Martin Poviser, Frank K. Gürkaynak, Luca Benini:
Basilisk: A 34mm² End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS : Integrated Systems Laboratory (ETH Zürich). 1-14 - Lucy Revina, Ethan Gao, Ken Ho, Daniel Lovell, Kristofer S. J. Pister, Borivoje Nikolic:
Taping Out Three Class Chips Per Semester in Intel 16 Technology. 1-53 - Idan Burstein:
ConnectX-8 SuperNIC. 1-21 - Kevin Chu:
AMD PensandoTM Pollara 400 AI NIC Architecture and Application. 1-35 - Darius Bunandar:
Passage M1000 : A 3D Photonic Interposer for AI. 1-34 - Mohamed Mehdi Jatlaoui, Jean-Marc Yannou:
High Density Si-IPD Technologies as Enabler for High-Performance and Low-Power Consumption Processor Chips. 1 - Ty Garibay, Shashank Nemawarkar:
Cuzco: A High-Performance RISC-V RVA23 Compatible CPU IP. 1-21 - Michael Matthews, Ian Winfield, Joseph Madril, Douglas De Aquino Castro, Charles Biset:
FABRIC8LABS Electrochemical Additive Manufacturing ECAM Enabled Thermal Solutions for the Al Data Center. 1-15 - Heng Liao:
UB-mesh: An New Interconnection Technology for Large AI SuperNode. 1-13 - Seokchan Song, Seryeong Kim, Wonhoon Park, Jongjun Park, Sanghyuk An, Gwangtae Park, Minseo Kim, Hoi-Jun Yoo:
IRIS: A 8.55 mJ/frame Spatial Computing SoC for Real-time Interactable-Rendering and Surface-aware-Modeling with 3D Gaussian Splatting. 1 - Seungjae Moon, Jung-Hoon Kim, Juntaek Oh, Jay Kim, Joo-Young Kim:
Adelia: A 4nm LLM Processor for Efficient Generative Al Inference. 1 - Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Toru Koizumi, Ryota Shioya, Kei Ishii:
PEZY-SC4s : The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI Applications. 1-42 - Tinish Bhattacharya, Dongseok Kwon, George Higgins Hutchinson, Xiangyi Zhang, Giacomo Pedretti, Fabian Böhm, John Paul Strachan, Thomas Van Vaerenbergh, Ray Beausoleil, Ignacio Rozada, Dmitri B. Strukov:
KLIMA: Low-latency mixed-signal In-Memory Computing accelerator for solving arbitrary-order Boolean Satisfiability. 1-7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-02 00:57 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
