default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th HPCA 2014: Orlando, FL, USA
- 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-3097-5
- George Kurian, Srinivas Devadas, Omer Khan:
Locality-aware data replication in the Last-Level Cache. 1-12 - Zhe Wang, Daniel A. Jiménez
, Cong Xu, Guangyu Sun, Yuan Xie:
Adaptive placement and migration policy for an STT-RAM-based hybrid cache. 13-24 - Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture. 25-36 - Cedric Nugteren, Gert-Jan van den Braak, Henk Corporaal, Henri E. Bal:
A detailed GPU cache model based on reuse distance theory. 37-48 - David J. Palframan, Nam Sung Kim, Mikko H. Lipasti:
Precision-aware soft error protection for GPUs. 49-59 - Raghuraman Balasubramanian, Karthikeyan Sankaralingam:
Understanding the impact of gate-level physical reliability effects on whole program execution. 60-71 - Ulya R. Karpuzcu, Ismail Akturk, Nam Sung Kim:
Accordion: Toward soft Near-Threshold Voltage Computing. 72-83 - Aditya Agrawal, Amin Ansari, Josep Torrellas:
Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules. 84-95 - Ruirui C. Huang, Erik Halberg, Andrew Ferraiuolo, G. Edward Suh:
Low-overhead and high coverage run-time race detection through selective meta-data management. 96-107 - Sotiria Fytraki, Evangelos Vlachos, Yusuf Onur Koçberber, Babak Falsafi, Boris Grot:
FADE: A programmable filtering accelerator for instruction-grain monitoring. 108-119 - Shanxiang Qi, Abdullah Muzahid, Wonsun Ahn, Josep Torrellas:
Dynamically detecting and tolerating IF-Condition Data Races. 120-131 - Wenli Zheng, Kai Ma, Xiaorui Wang:
Exploiting thermal energy storage to reduce data center capital and operating expenses. 132-141 - Daniel Wong, Murali Annavaram:
Implications of high energy proportional servers on cluster-wide energy proportionality. 142-153 - Marisabel Guevara, Benjamin Lubin, Benjamin C. Lee:
Strategies for anticipating risk in heterogeneous system design. 154-164 - Marco Elver, Vijay Nagarajan:
TSO-CC: Consistency directed cache coherence for TSO. 165-176 - Socrates Demetriades, Sangyeun Cho:
Stash directory: A scalable directory for many-core coherence. 177-188 - Blake A. Hechtman, Shuai Che, Derek R. Hower, Yingying Tian, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, David A. Wood:
QuickRelease: A throughput-oriented approach to release consistency on GPUs. 189-200 - Jesse Elwell, Ryan Riley, Nael B. Abu-Ghazaleh, Dmitry Ponomarev:
A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks. 201-212 - Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk, Omer Khan, Srinivas Devadas:
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs. 213-224 - Yao Wang, Andrew Ferraiuolo, G. Edward Suh:
Timing channel protection for a shared memory controller. 225-236 - Amro Awad, Yan Solihin:
STM: Cloning the spatial and temporal memory access behavior. 237-247 - Ahmed ElTantawy, Jessica Wenjie Ma, Mike O'Connor, Tor M. Aamodt:
A scalable multi-path microarchitecture for efficient GPU control flow. 248-259 - Minseok Lee, Seokwoo Song, Joosik Moon, John Kim, Woong Seo, Yeon-Gon Cho, Soojung Ryu:
Improving GPGPU resource utilization through alternative thread block scheduling. 260-271 - Wenhao Jia, Kelly A. Shaw, Margaret Martonosi:
MRPB: Memory request prioritization for massively parallel processors. 272-283 - Ping Xiang, Yi Yang, Huiyang Zhou:
Warp-level divergence in GPUs: Characterization, impact, and mitigation. 284-295 - Lizhong Chen, Lihang Zhao, Ruisheng Wang, Timothy Mark Pinkston:
MP3: Minimizing performance penalty for power-gating of Clos network-on-chip. 296-307 - Jae-Yeon Won, Xi Chen, Paul Gratz, Jiang Hu, Vassos Soteriou:
Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management. 308-319 - Dominic DiTomaso, Avinash Karanth Kodi, Ahmed Louri:
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers. 320-331 - Hanjoon Kim, Gwangsun Kim, Seungryoul Maeng, Hwasoo Yeo, John Kim:
Transportation-network-inspired network-on-chip. 332-343 - Mingli Xie, Dong Tong, Kan Huang, Xu Cheng:
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning. 344-355 - Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu:
Improving DRAM performance by parallelizing refreshes with accesses. 356-367 - Tao Zhang, Matthew Poremba, Cong Xu, Guangyu Sun, Yuan Xie:
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. 368-379 - Wei Wang, Tanima Dey, Jack W. Davidson, Mary Lou Soffa:
DraMon: Predicting memory bandwidth usage of multi-threaded programs with high accuracy and low overhead. 380-391 - Meng Zhang, Jesse D. Bingham, John Erickson, Daniel J. Sorin:
PVCoherence: Designing flat coherence protocols for scalable verification. 392-403 - Dibakar Gope, Mikko H. Lipasti:
Atomic SC for simple in-order processors. 404-415 - Yutao Liu, Yubin Xia, Haibing Guan, Binyu Zang, Haibo Chen:
Concurrent and consistent virtual machine introspection with hardware transactional memory. 416-427 - Arthur Perais, André Seznec:
Practical data value speculation for future high-end processors. 428-439 - Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas:
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. 440-451 - Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jiménez:
Improving cache performance using read-write partitioning. 452-463 - Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-Sup Kim:
NUAT: A non-uniform access time memory controller. 464-475 - Tomas Karnagel, Roman Dementiev, Ravi Rajwar, Konrad Lai, Thomas Legler, Benjamin Schlegel, Wolfgang Lehner:
Improving in-memory database index performance with Intel® Transactional Synchronization Extensions. 476-487 - Lei Wang, Jianfeng Zhan, Chunjie Luo, Yuqing Zhu, Qiang Yang, Yongqiang He, Wanling Gao, Zhen Jia, Yingjie Shi, Shujie Zhang, Chen Zheng, Gang Lu, Kent Zhan, Xiaona Li, Bizhu Qiu:
BigDataBench: A big data benchmark suite from internet services. 488-499 - Philip G. Emma, Alper Buyuktosunoglu, Michael B. Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime H. Moreno, Eren Kursun:
3D stacking of high-performance processors. 500-511 - Sudarsun Kannan, Ada Gavrilovska, Karsten Schwan:
Reducing the cost of persistence for nonvolatile heaps in end user devices. 512-523 - Myoungsoo Jung, Mahmut T. Kandemir:
Sprinkler: Maximizing resource utilization in many-chip solid state disks. 524-535 - Kai Zhao, Kalyana S. Venkataraman, Xuebin Zhang, Jiangpeng Li, Ning Zheng, Tong Zhang:
Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs. 536-545 - Youngsok Kim, Jaewon Lee, Jae-Eon Jo, Jangwoo Kim:
GPUdmm: A high-performance and memory-oblivious GPU architecture using dynamic memory management. 546-557 - Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh:
Increasing TLB reach by exploiting clustering in page translations. 558-567 - Jason Power, Mark D. Hill, David A. Wood:
Supporting x86-64 address translation for 100s of GPU lanes. 568-578 - Opeoluwa Matthews, Meng Zhang, Daniel J. Sorin:
Scalably verifiable dynamic power management. 579-590 - Mitchell Hayenga, Vignyan Reddy Kothinti Naresh, Mikko H. Lipasti:
Revolver: Processor architecture for power efficient loop execution. 591-602 - David Lo, Christos Kozyrakis:
Dynamic management of TurboMode in modern multi-core chips. 603-613 - Nagesh B. Lakshminarayana, Hyesoon Kim:
Spare register aware prefetching for graph algorithms on GPUs. 614-625 - Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian:
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. 626-637 - Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian, Al Davis:
MemZip: Exploring unconventional benefits from memory compression. 638-649 - Hung-Wei Tseng, Dean M. Tullsen:
CDTT: Compiler-generated data-triggered threads. 650-661 - Raj Parihar, Michael C. Huang:
Accelerating decoupled look-ahead via weak dependence removal: A metaheuristic approach. 662-677 - Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout:
Undersubscribed threading on clustered cache architectures. 678-689
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-02-06 22:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
