default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID43rd ICCD 2025: Richardson, TX, USA
- 43rd IEEE International Conference on Computer Design, ICCD 2025, Richardson, TX, USA, November 10-12, 2025. IEEE 2025, ISBN 979-8-3315-0346-8
- Yujin Kim, Chanhun Jeong, Yunho Oh, Myung Kuk Yoon, Gunjae Koo:
FINEA: An Efficient Neural Network Accelerator Exploiting Factorized Input Features. 1-9 - Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing, Qin Wang:
RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V. 1-8 - Rostin Shokri, Charles Gouert, Nektarios Georgios Tsoutsos:
HElix: Genome Similarity Detection in the Encrypted Domain. 1-8 - Jinlei Hu, Bo Chen, Miaosong Zhang, Jing Hu, Jianxi Chen, Dan Feng:
R2Hash: A Read-Optimized and Resize-Friendly Hashing Index for Persistent Memory. 1-9 - Banafsheh Saber Latibari, Najmeh Nazari, Hossein Sayadi, Houman Homayoun, Abhijit Mahalanobis:
Hammering the Diagnosis: Rowhammer-Induced Stealthy Trojan Attacks on ViT-Based Medical Imaging. 1-8 - Yubiao Huang, Peinan Li, Huan Qiao, Yunkai Bai, Shiwen Wang, Dan Meng, Rui Hou:
Tips: Augment Memory Tagging to Defend Against Prefetcher Side Channels. 1-8 - Jhon Ordoñez, Chengmo Yang:
Targeted Fault Injection Attack on Semantic Segmentation Models. 9-16 - Zhixin Pan, Ziyu Shu, Amberbir Alemayoh:
Towards Low-Latency and Adaptive Ransomware Detection Using Contrastive Learning. 17-24 - Xuanyao Peng, Yinghao Yang, Shangjie Pan, Junjie Huang, Yujun Liang, Hang Lu, Fengwei Zhang, Xiaowei Li:
SecNPU: Securing LLM Inference on NPU. 25-32 - Yu-Chih Tsai, Chia-Cheng Chang, Ren-Shuo Liu:
DMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision Adjustment. 33-40 - Chandan Kumar N. S, Bhavana S, Ajitesh Kumar Singh, Madhav Rao:
Hardware Efficient Multiplier Design Using an Optimal Mix of Approximate Booth Encodings. 41-48 - Zhenzhen Jia, Hongbing Tan, Ling Yang, Hui Guo, Kun Zeng, Junsheng Chang, Yongwen Wang, Libo Huang:
PolyPE: An Efficient Multi-Precision Multi-Mode Floating-Point Processing Element for HPC and AI. 49-56 - Yu Ma, Jianmin Zhang, Yan Sun, Siqing Fu:
CHQ-SC: Compact and High-Quality Stochastic Computing Framework Using Magnetic Tunnel Junction. 57-60 - Xu Dai, Dehao Kong, Xufeng He, Zijun Xu, Shaopeng Zhai, Yang Hu, Shouyi Yin:
RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale Computing. 61-69 - Haiquan Wang, Chaoyi Ruan, Jia He, Jiaqi Ruan, Chengjie Tang, Xiaosong Ma, Cheng Li:
DHeLlam: General-Purpose, Automatic Micro-Batch Co-Execution for Distributed LLM Training. 70-78 - Yuan Zhang, Huawei Cao, Yiming Sun, Ming Dun, Jie Zhang, Xiaochun Ye:
A Co-Design Framework for Graph Processing on CPU-GPU Heterogeneous Platforms. 79-86 - Tong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang, Chunming Hu:
Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms. 87-94 - Zhenqi Li, Yuan Li, Mingche Lai, Puguang Liu, Qiang Wang, Yankang Zhao, Hanyuan Li, Xingyun Qi:
Enhancing Transformer Inference Efficiency on FPGA Through Fully Fusion and Integer-Only Quantization Techniques. 95-102 - Lei Zhao, Aishwarya Natarajan, Luca Buonanno, Archit Gajjar, Ron M. Roth, Sergey Serebryakov, John Moon, Omar Eldash, Jim Ignowski, Giacomo Pedretti:
RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration. 103-110 - Arpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti, Luca Benini:
PACE-Lite: Compact and Efficient Piecewise Polynomial Approximation for Transformer Nonlinearity Acceleration. 111-118 - Adrián Navarro, José Cano, José L. Abellán, Manuel E. Acacio:
QuFi: Adaptive Tiled Gustavson Output Reuse for Edge Sparse DNN Accelerators. 119-126 - Sangwon Shin, Ngoc-Son Pham, Lei Xu, Weidong Shi, Taeweon Suh:
HBM-Aware Number Theoretic Transform Accelerator for Zero-Knowledge Proof. 127-130 - Jiahui Zhang, Qiang Cao, Yekang Zhan, Yuchen Hu, Jie Yao:
Repo: Proactive Swapping Exploiting Loop Patterns in Modern Applications. 131-138 - Yuquan Chi, Yinjin Fu, Nong Xiao:
RT-PMalloc: Optimizing Persistent Memory Allocation for Soft Real-Time Systems. 139-146 - Gyusun Lee, Seungwoo Jin, Jiwon Woo, Jinkyu Jeong:
A Scalable and Overflow-Tolerant Mechanism for Minimum Virtual Time Tracking. 147-154 - Qingqiu Lan, Ao Ren, Zhenyu Wang, Wei Li, Hongbin Zhu, Yujuan Tan, Duo Liu, Kan Zhong, Chaoxia Qin:
CAST: An Efficient Framework for Schedules Performance Prediction Based on Compact ASTs. 155-158 - Varun Darshana Parekh, Zachary Wyatt Hazenstab, Srivatsa Rangachar Srinivasa, Krishnendu Chakrabarty, Kai Ni, Vijaykrishnan Narayanan:
STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration. 159-166 - Shan Shen, Xingyang Li, Zhuohua Liu, Junhao Ma, Yikai Wang, Yiheng Wu, Yuquan Sun, Wei W. Xing:
OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite. 167-175 - George Goudroumanis, Maria Pantazi-Kypraiou, George Floros, Athanasios Tziouvaras, Georgios I. Stamoulis, Alberto García-Ortiz:
3DPX - An Open-Source Methodology for 3D Physical Design Exploration. 176-179 - Fang Li:
Declarative Synthesis and Multi-Objective Optimization of Stripboard Circuit Layouts Using Answer Set Programming. 180-183 - Qiyang Zheng, Hao Hu, Hao Huang, Yanqi Pan, Yifeng Zhang, Wen Xia, Xiangrui Meng, Xudong Li:
ALPHA: A Scalable Lock-Free Partitioned Hash Index for Persistent Memory on NUMA Architectures. 193-200 - Taejeong Kim, Junbum Park, Yongho Lee, Seokin Hong:
DDLM: Demand-Aware Dynamic Link Width Management for Energy-Efficient CXL Memory. 201-208 - Choongseok Song, Doo Seok Jeong:
Computing-in-Memory Dataflow for Minimal Buffer Traffic. 209-216 - Junsung Kim, Sungwoo Kim, Seunghyun Jin, Won Woo Ro:
PIMFY: Eliminating Remote Page Walks in MCM GPUs. 217-220 - Junghyeok Lee, Jihoon Jang, Hyun Kim:
PriME: PIM-Aware Efficient Compression for Memory-Bound Embedding Layers in sLLMs. 221-228 - Ming Han, Jin Wu, Jian Dong, Ye Wang, Gang Qu:
CMC: Compound Memory-Computing Architecture for Energy-Efficient CNN Accelerators. 229-236 - Yongjoo Jang, Sangwoo Hwang, Hojin Lee, Sangwoo Jung, Donghun Lee, Wonbo Shim, Jaeha Kung:
Dissecting and Re-Architecting 3D NAND Flash PIM Arrays for Efficient Single-Batch Token Generation in LLMS. 237-244 - Mingzi Li, Zhongrui Wang, Zhongwen Ye, Tao Pan, Han Wang:
MamCIMFlow: An Integrated Co-Design of RRAM-Based CIM and Selective State-Space Streaming for Efficient Mamba Model Acceleration. 245-248 - Fan Li, Ruizhi Zhu, Huize Li, Di Wu, Xin Xin:
PIM-SUM: Fast and Reliable In-Memory Summation for Recommendation Systems. 249-252 - Jinhui Wei, Ye Huang, Yuhui Zhou, Jiazhi Jiang, Jiangsu Du:
Ghidorah: Fast LLM Inference on Edge with Speculative Decoding and Hetero-Core Parallelism. 253-260 - Yujuan Tan, Jiayi Guo, Zhuoxin Bai, Sanle Zhao, Yujiao Wang, Zongjie Wang, Ao Ren, Kan Zhong, Lin Huang, Jun Liu:
DualSpar: A Dual-Granularity Memory Framework with Adaptive Sparsity for Efficient LLM Inference. 261-268 - Sanghyeon Lee, Hongbeen Kim, Soojin Hwang, Guseul Heo, Minwoo Noh, Jaehyuk Huh:
Throughput-Oriented LLM Inference via KV-Activation Hybrid Caching with A Single GPU. 269-276 - Xiao Shi, Jiangsu Du, Zhiguang Chen, Yutong Lu:
AuLoRA: Fine-Grained Loading and Computation Orchestration for Efficient LoRA LLM Serving. 277-284 - Pragya Sharma, Ashish Reddy Bommana, Farshad Firouzi, Krishnendu Chakrabarty:
Taming Sparse Giants: Deploying Mixture-of-Experts on 3D Heterogeneous Compute-in-Memory Systems. 285-288 - Boru Chen, Rutvik Choudhary, Kaustubh Khulbe, Archie Lee, Adam Morrison, Christopher W. Fletcher:
$\mu\text{STT}$: Microarchitecture Design for Speculative Taint Tracking. 289-297 - Ziyue Zheng, Zhiyuan Yan, Xiangchen Meng, Guangyu Hu, Hongce Zhang, Yangdi Lyu:
Hot-FV: A Semi-Formal Test Generation Framework for RTL Functional Coverage Using Warm Starting States. 298-305 - Yumei Hu, Hairui Cai, Xiaohui Xue, Yaning Wang, Yu Huang, Zhipeng Lv, Zhouxing Su, Zezhong Wang, Xing Wang:
ATPG-Based Weighted Scan Chain Control for Programmable Low-Power LBIST. 306-314 - Venkat Nitin Patnala, Sai Manoj Pudukotai Dinakarrao:
FitFuzz: Depth-Oriented Coverage-Guided Fuzzing via Fitness-Based Seed Scheduling. 315-318 - Yue Jin, Yibin Xu, Han Wang, Chengyuan Zhang, Tianyi Huang, Tianyue Lu, Mingyu Chen:
DASICS: Efficient In-Process Protection with Hardware-Assisted Dynamic Compartmentalization. 319-322 - Hongyu Zhang, Yuntao Liu:
Security Evaluation of Quantum Circuit Split Compilation Under an Oracle-Guided Attack. 323-328 - Rupshali Roy, Swaroop Ghosh:
Forensics of Error Rates of Quantum Hardware. 329-334 - Ben Dong, Hui Feng, Qian Wang:
QTIME: A Machine Learning Framework for Timing Side-Channel Analysis in Quantum Circuit Simulators. 335-341 - Kidus Tessma, Hrvoje Kukina, Jakub Szefer:
Recovering QSVT Polynomials from Side-Channel Information on Quantum Computers. 342-347 - Navnil Choudhury, Ameya S. Bhave, Kanad Basu:
Concolic Testing for Quantum Compilers. 348-355 - Priyabrata Senapati, Shengye Zhu, Bo Peng, Bo Fang, Qiang Guan:
UQ-VarQA: Benchmarking and Characterizing NISQ Computers Through Uncertainty Quantification of Variational Quantum Algorithms. 356-363 - Mingyang Kou, Jun Zeng, Xinyu Peng, Weiqing Ji, Hailong Yao:
NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA Mapping. 364-371 - Heming Zhong, Jinhui Wei, Yujia Fu, Dan Huang, Yutong Lu:
IasRT: Interference-Aware and SLO-Driven GPU Scheduling for Real-Time DNN Inference. 372-379 - Bo Yuan, Sheng Liu, Zekun Jiang, Jianfeng Cui, Yang Guo:
AICAWS: Arithmetic Intensity Based Cache-Conscious Adaptive Warp Scheduler. 380-388 - Gaolin Wei, Zhaorui Zhang, Jiaqi Xu, Chen Jason Zhang, Xin Yao, Benben Liu:
A Dynamic Virtual Memory Management System for LLMs on AI Chips. 389-392 - Mingxiao He, Pengcheng Huang, Zhenyu Zhao, Peiyun Bian:
CPA-Remap: Critical-Path-Based Physically Aware Remapping Framework for Timing Optimization. 393-400 - Jaejoon Yoon, Taewhan Kim:
Threshold Voltage Tuning Technique for Leakage Power Recovery. 401-408 - Youzhi Zheng, Zhengjie Zhao, Linhao Lu, Xiaodong Zhu, Wenxin Yu, Jingwei Lu:
Timing-Driven Global Placement with Entropy-Mobility Guided Pin-to-Pin Weighting. 409-415 - Yeongyeong Shin, Sehyeon Chung, Taewhan Kim:
Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques. 416-423 - Emilien Meyer, Abu Kaisar Mohammad Masum, Mehran Shoushtari Moghadam, Lida Kouhalvandi, Gourav Datta, Sercan Aygun, M. Hassan Najafi:
GAN-BiLSTM-HDC: A Hybrid Framework for Robust and Hardware-Efficient Malware Detection. 424-431 - Ahmad Tahmasivand, Noureldin Zahran, Saba Al-Sayouri, Mohamed E. Fouda, Khaled N. Khasawneh:
LM-Fix: Lightweight Bit-Flip Detection and Rapid Recovery Framework for Language Models. 432-440 - Najmeh Nazari, Banafsheh Saber Latibari, Elahe Hosseini, Fatemeh Movafagh, Chongzhou Fang, Hosein Mohammadi Makrani, Kevin Immanuel Gubbi, Abhijit Mahalanobis, Setareh Rafatirad, Hossein Sayadi, Houman Homayoun:
FaRAccel: FPGA-Accelerated Defense Architecture for Efficient Bit-Flip Attack Resilience in Transformer Models. 441-449 - Qiao Li, Hong Jiang, Yucheng Zhang, Zichen Xu, Junyun Wu, Puchen Lu:
Hybrid-Rewrite: A Rewriting Framework for Hybrid Deduplication and Delta Compression. 458-465 - Jinlong Wang, Zhipeng Tan, Yang Xiao, Wenjie Qi, Shikai Tan, Ying Yuan:
NatSep: Little-to-No Overhead Data Separation for Log-Structured Storage Using Native Information. 466-473 - Cai Deng, Boju Chen, Philip Shilane, Xiangyu Zou, Wen Xia, Hao Hu:
The Logic of Fingerprint Upgrade in Deduplicated Storage. 474-481 - Alex Sensintaffar, David Du, Bingzhe Li:
Pixel-DNA: Increasing Robustness of Approximate DNA Storage for Images by Using Hierarchical Deduplication. 482-490 - Habib Ur Rahman, Tharini Suresh, Sudeep Pasricha, Biswajit Ray:
TCFlash: In-Flash Bulk Bitwise Processing via Dynamic Sensing and TLC Encoding in 3D NAND. 491-494 - Joonseong Hwang, Minkyu Choi, Minjin Park, Jihun Yoon, Yoonho Jang, Seokin Hong:
Minimizing Read Disturb via Localized Page Allocation for Modern NAND Flash-Based SSDs. 495-498 - Davide Baroffio, Tomas Antonio Lopez, Federico Reghenzani, William Fornaciari:
Laser and Radiation Testing of Compiler-Based Protection for Multi-Bit Upsets. 499-506 - Shuyi Chen, Jingdian Ming, Yuejun Liu, Yiwen Gao, Yongbin Zhou:
Masked Gadgets for Integer-Floating-Point Conversion with Applications to Falcon. 507-514 - Ntsee Ndingwan, Chengmo Yang:
WSSR: Weight Set Segmentation and Recovery for Fault Resilient Transformers. 515-522 - Ishraq Tashdid, Dewan Saiham, Nafisa Anjum, Tasnuva Farheen, Sazadur Rahman:
ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs. 523-527 - Denis Nabokov, Xiaofei Tong, Qian Guo:
Enhancing Key-Recovery Chosen-Ciphertext Side-Channel Attacks on NTRU Using LDPC. 528-531 - Yuan Li:
A Photonic Accelerator for Deep Learning Training. 532-539 - Ao Lyu, Haishuang Fan, Guihai Yan:
Flame: A Multiplier-Free LLM Accelerator with Dynamic Block Floating Point. 549-557 - Rui Meng, Xinyu Chen, Hanyue Lin, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
Hermes: Accelerating Packet Processing in DPU with Neural Network. 558-561 - Zijian Xiong, Xiangrui Yang, Yuhang Zhang, Yue Zhou, Jianguo Yang, Yaoyu Tao, Xiangshui Miao, Yuhui He:
ASMA: An Anisotropy Scaling Memristor-Based Accelerator for LLM Inference. 562-565 - Zhigang Fang, Renzhi Chen, Yang Guo, Huadong Dai, Lei Wang:
RTLBench: A Multi-Dimensional Benchmark Suite for Evaluating LLM-Generated RTL Code. 566-573 - M. Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali:
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation. 574-581 - Asmita, Grisha Bandodkar, Sujan Ghimire, Shaurya Srivastav, Soheil Salehi, Houman Homayoun:
Llm4mcu-Onto: Leveraging Llms for Automated Ontology Generation From Microcontroller Reference Manual. 582-589 - Rupesh Raj Karn, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu:
LLM-Driven Code Generation for Neural Networks on FPGAs: Bridging Python and HLS. 590-593 - Navaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti, Luca Benini:
TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads. 594-601 - Yichao Zhang, Zexin Fu, Tim Fischer, Yinrong Li, Marco Bertuletti, Luca Benini:
TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters. 610-617 - Yanze Wu, Md Tanvir Arafin:
Thena: Torus Fully Homomorphic Encryption on Energy-Efficient Heterogeneous Architecture. 618-625 - Sho Ko, Kunle Olukotun:
SSM-RDU: A Reconfigurable Dataflow Unit for Long-Sequence State-Space Models. 626-629 - Pei-Huan Tsai, Maico Cassel dos Santos, Joseph Zuckerman, Kuan-Lin Chiu, Luca P. Carloni:
Optimization of Wire Pipelining and Channel Parallelism for 2D-Mesh NoC Physical Design. 630-637 - Liming Deng, Guowei Zhu, Wei Cao, Xitian Fan, Xuegong Zhou:
Agile Design Flow for Cryptographic Hardware Accelerators. 638-645 - Feng-Jie Chao, Yung-Chih Chen:
Decomposition Attack on Structural Logic Locking of Reversible Circuits. 646-653 - Essien Taylor, Colin Schilf, Sebastian Phemister, Russ Joseph:
Supporting Pipelined Memory Accesses in Processor Synthesis. 654-657 - Zijun Jiang, Yangdi Lyu:
BNRV: A Lightweight SIMD Extension for Efficient BitNet Inference on RISC-V CPUs. 658-665 - Omer Karslioglu, Ismail Akturk:
Design and Evaluation of an N-Trace Compliant Hardware Tracer for RISC-V Processors. 666-673 - Junpei Huang, Haobo Xu, Ying Wang, Yinhe Han:
FlexIO: A Scalable IO Chiplet Architecture with Flexible Memory Controller Mapping. 674-681 - Fan Yang, Toru Koizumi, Jun Li, Shu Sugita, Yuriko Yamauchi, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie:
Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors. 682-689 - Fanchen Kong, Yunhao Deng, Xiaoling Yi, Ryan Antonio, Marian Verhelst:
XDMA: A Distributed, Extensible DMA Architecture for Layout-Flexible Data Movements in Heterogeneous Multi-Accelerator SoCs. 690-693 - Hongyan Li, Jinkai Zhang, Hang Lu, Xiaowei Li:
AceHomo: Accelerating Privacy Preserving Inference Through Dynamic Level Adjustment. 694-701 - Shriniwas Kulkarni, Flavio Ponzina, Tajana Rosing:
HyperDrone: An Accurate, Robust, Fast, and Energy-Efficient Approach for Drone Classification. 702-709 - Chia-Chun Wang, Chuan-Yao Lai, Ren-Shuo Liu:
Access Frequency-Aware Storage Reduction for Deep Learning Recommendation Model. 710-717 - Yu Chen, Wenli Zheng:
Recommendation-Expert Framework for Fast and Adaptive Scheduling in Computing Power Network. 718-725 - Zhaoxiang Huang, Jianqin Yan, Hao Chen, Jiaxin Li, Yiming Zhang:
Oak: A Fault-Tolerant Shared-Memory System Atop Memory-Semantic Fabrics. 726-729 - Dengke Han, Duo Wang, Mingyu Yan, Xiaochun Ye, Dongrui Fan:
TLV-HGNN: Thinking Like a Vertex for Memory-Efficient HGNN Inference. 730-737 - Yuchen Gui, Wei Yuan, Qizhe Wu, Huawen Liang, Letian Zhao, Linfeng Tao, Zhongguang Xu, Xi Jin:
SageSC: Accelerating GraphSAGE Minibatch Inference on Memory-Intensive Graphs. 738-745 - Ismail Emir Yüksel, Ataberk Olgun, F. Nisa Bostanci, Oguzhan Canpolat, Geraldo F. Oliveira, Mohammad Sadrosadati, A. Giray Yaglikçi, Onur Mutlu:
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips. 754-763 - Wenkai Wang, Chao Liu, Zhe Sun, Lei Ju, Zimeng Zhou:
Adaptive ML-KEM: A Configurable HW-SW Architecture for Post-Quantum Cryptography. 764-767 - Sudipta Paria, Aritra Dasgupta, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia:
FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation. 768-775 - Matthew DeLorenzo, Kevin Tieu, Jeyavijayan Rajendran:
Tracing the Logic: Evaluating LLM Reasoning Paths in RTL Generation. 776-781 - Jonti Talukdar, Agastya Seth, Sanmitra Banerjee, Farshad Firouzi, Krishnendu Chakrabarty:
MALLS: Multi-Agent LLMs for Synthetic Hardware Vulnerability Generation and Detection. 782-789 - Nowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar:
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage. 790-797 - Haoyuan Zhang, Yaqian Gao, Xinxin Zhang, Jialin Li, Runfeng Jin, Yidong Chen, Feng Zhang, Wu Yuan, Wenpeng Ma, Shan Liang, Jian Zhang, Zhonghua Lu:
FlashMP: Fast Discrete Transform-Based Solver for Preconditioning Maxwell's Equations on GPUs. 798-806 - Shuang Yang, Yaobin Wang, Ling Li, Qian Peng, Qiong Yu:
MH-SpGEMM: Efficient Sparse General Matrix-Matrix Multiplication on Modern GPUs via Masking and Hashing Cooperative Optimization. 807-814 - Jieran Zhang, Bizhao Shi, Guojie Luo:
TensTFM: Efficient Total Focusing Method for Ultrasonic Array Imaging on Dataflow Accelerators. 815-822 - Takuya Kasamura, Junichiro Kadomoto, Hidetsugu Irie:
Design of an Online Surface Code Decoder Using Union-Find Algorithm. 823-830 - Emir Eryilmaz, Selim Sandal, Ismail Akturk:
Early Termination with Activation Sign Prediction for Energy-Efficient CNN Inference Using Sum-of-Power-of-Two Quantization. 831-834 - Tharini Suresh, Salma Afifi, Sudeep Pasricha:
Sustainable Acceleration of Generative AI Neural Network Models with Silicon Photonics. 835-842 - Ziang Yin, Hongjian Zhou, Chetan Choppali Sudarshan, Vidya A. Chhabria, Jiaqi Gu:
Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and Robustness. 843-850 - Dharanidhar Dang:
SUSTAINPHOT: Sustainable Large-Scale AI Training Using Analog Silicon Photonic Accelerators. 851-858 - Ishan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo:
Scaling Up the Sustainability of Photonic Tensor Cores With Device-Circuit-Signaling Co-Design. 859-866 - Pratik Shrestha, Ioannis Savidis:
Representation Learning for Digital Integrated Circuit Design Automation. 867-871 - Olivera Kotevska, Wenjun Yang, Eyhab Al-Masri:
Engineering Privacy at the Edge: A Practical Guide to Differential Privacy in System Architectures. 872-875
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-01-18 01:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
