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ORCIDISCAS 1994: London, UK - Volume 4
- 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994. IEEE 1994, ISBN 0-7803-1916-8
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS
- Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan:
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. 1-6
Circuit Techniques
- Richard X. Gu, Mohamed I. Elmasry:
An All-N-Logic High-Speed Single-Phase Dynamic CMOS Logic. 7-10 - Qiuting Huang, Robert Rogenmoser:
A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications. 11-14 - Hong-Yi Huang, Chung-Yu Wu:
New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. 15-18 - Khaled M. Sharaf, Mohamed I. Elmasry:
BiCMOS Active-Pull-Down Non-Threshold Logic Cicuits for High-Speed Low-Power Applications. 19-22 - Yuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu:
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit. 23-26 - Todd C. Weigandt, Beomsup Kim, Paul R. Gray:
Analysis of Timing Jitter in CMOS Ring Oscillators. 27-30 - Beomsup Kim, Todd C. Weigandt, Paul R. Gray:
PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. 31-34 - Sven Simon, Ernst G. Bernard, Matthias Sauer, Josef A. Nossek:
A New Retiming Algorithm for Circuit Design. 35-38
(Posters): VLSI Designs
- V. K. Raj, R. V. Idate, A. W. Booth, M. Botlo, J. Dorenbosch, E. C. Milner, E. M. Wang:
Design of an ASIC to Implement a New Data Tranfer Protocol for High Energy Physics. 39-42 - Jacob Midtgaard, Christer Svensson:
5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOS. 43-46 - Kyung-Wook Shin, Heung-Woo Jeon, Yong-Seum Kang:
An Efficient VLSI Implementation of Vector-Radix 2-D DCT using Mesh-Connected 2-D Array. 47-50 - Nianxiong Tan, Sven Eriksson, Lars Wanhammar:
A Power-Saving Technique for Bit-Serial DSP ASICs. 51-54 - Maher N. Fahmi, Fayez El Guibaly, Sreenivasachar Sunder, Dale J. Shpak:
Design of Novel Serial-Parallel Inner-Product Processors. 55-58 - June Wang, Zhongde Wang, Graham A. Jullien, William C. Miller:
Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic. 59-62 - Naim Ben-Hamida, Bozena Kaminska, Yvon Savaria:
Pseudo-Random Vector Compaction for Sequential Testability. 63-66 - Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda:
A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. 67-70 - Arun Ramaswamy, Wasfy B. Mikhael:
An Efficient Coding Technique for Multi-Transform Image Representation. 71-74 - Mohsin M. Jamali, S. Ravindranath, Subhash C. Kwatra, A. G. Eldin:
ASIC Design of a Generalized Covariance Matrix Processor for DOA Algorithms. 75-78 - Vassilis Paliouras
, Thanos Stouraitis:
Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors. 79-82 - Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
CMOS Reliability Improvements Through a New Fault Tolerant Technique. 83-86 - Randy E. Bolling, Sami A. Al-Arian:
Reconfigurable Linear Feedback Register Design, Analysis & Applications. 87-90
Analogue VLSI
- Mohammad Hossein Shakiba, David A. Johns, Kenneth W. Martin:
Analog Implementation of Class-IV Partial-Response Viterbi Detector. 91-94 - Jaime Ramírez-Angulo, Kevin Treece, Mark DeYong:
Real Time Solution of Laplace equation using Analog VLSI Circuits. 95-98 - James E. C. Brown, Paul J. Hurst, Lawrence Der, Iskender Agi:
A Comparison of Analog DFE Architectures for Disk-Drive Applications. 99-102 - Robin Woodburn, H. Martin Reekie, Alan F. Murray:
Pulse-Stream Circuits for On-Chip Learning in Analogue VLSI Neural Networks. 103-106 - Andrea Baschirotto, M. Bosetti, Rinaldo Castello, Alberto Gola, Gianluigi Ezio Pessina, Pier Giorgio Rancoita, M. Rattaggi, M. Redaelli, G. Terzi:
High Speed Monolithic Read-Out System for High Energy Physics Experiments. 107-110 - Brian S. Cherkauer, Eby G. Friedman:
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. 111-114 - Chong-Gun Yu, Randall L. Geiger:
An Accurate and Matching-Free Threshold Voltage Extraction Scheme for MOS Transistors. 115-118 - Shih-Chii Liu, Carver Mead:
Continuous-Time Adaptive Delay System. 119-122 - Diego Vázquez, Adoración Rueda, José L. Huertas:
A Low-Cost Strategy for Testing Analog Filters. 123-126
Architecture & Application I
- Martin Vaupel, Heinrich Meyr:
High Speed FIR-Filter Architectures with Scalable Sample Rates. 127-130 - Srikanth Karkada, Chaitali Chakrabarti, Andreas Spanias:
High Sample Rate Architectures for Block Adaptive Filters. 131-134 - Hubert Harrer, Josef A. Nossek, Tamás Roska, Leon O. Chua:
A Current-Mode DTCNN Universal Chip . 135-138 - Chung-Wei Ku, Liang-Gee Chen, Tzi-Dar Chiueh, Her-Ming Jong:
Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms. 139-142 - Fabian Klass, Michael J. Flynn, Ad J. van de Goor:
A 16x16-bit Static CMOS Wave-Pipelined Multiplier. 143-146 - Ren-Yang Yang, Chen-Yi Lee:
High-Throughput Data Compressor Designs Using Content Addressable Memory. 147-150 - Karel Adriaensen, Pascal Roobrouck:
Synchronous Traffic to Asynchronous Switch-Fabric Shaper. 151-154 - An-Yeu Wu, K. J. Ray Liu:
A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. 155-158 - Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke:
Virtual Hardware and the Limits of Computational Speed-up. 159-162
Forum: Wave-pipelining: Is it Practical?
- Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski:
Forum: Wave-pipelining: Is it Practical? 163-166
Design 1
- Sheng-Chieh Huang, Liang-Gee Chen, Thou-Ho Chen:
The Chip Design of A 32-b Logarithmic Number System. 167-170 - Wen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung:
On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design. 171-174 - José Luis Neves, Eby G. Friedman:
Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. 175-178 - Jaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar:
High Performance CMOS Macromodule Layout Synthesis. 179-182 - Paul-Waie Shew, Jin-Tai Yan, Pei-Yung Hsiao, Yong-Ching Lim:
Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing. 183-186 - Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam:
An Efficient Four Layer Over-the-Cell Router. 187-190 - Pramod Anne, Aditya Reddy, Naveed A. Sherwani, Anand Panyam, Siddharth Bhingarde:
Comparative Analysis of New CMOS Leaf Cells for OTC Routing. 191-194 - H. J. Kadim, G. E. Taylor:
Logic Value Assignment Contribution to Testability Analysis. 195-198 - Sami A. Al-Arian, Randy E. Bolling:
Improving the Testability of VLSI Circuits through Partitioning. 199-202
VLSI Architectures
- Shyue-Win Wei:
VLSI Architectures for Computing Exponentiations, Multiplicative Inverses, and Divisions in GF(2m). 203-206 - Lori Lucke, Chaitali Chakrabarti:
A Digit-Serial Architecture for Gray-Scale Morphological Filtering. 207-210 - Jongseob Baek, Seunghyun Nam, Moonkey Lee, Chuldong Oh, Kisoo Hwang:
A Fast Array Architecture for Block Matching Algorithm. 211-214 - Gagan Gupta, Chaitali Chakrabarti:
VLSI Architectures for Hierarchical Block Matching. 215-218 - Patricia Planet, Gilles Privat:
Convergence Control of Relaxation Processes with Fine-Grain Locally-Connected Two-Scale Automata Networks. 219-222 - Kamal Nourji, Nicolas Demassieux:
Optimization of Real-Time VLSI Architectures for Distributed Arithmetic-Based Algorithms: Application to HDTV Filters. 223-226 - Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass:
Partitioning and Retiming of Multi-Dimensional Systems. 227-230 - Takayuki Sagishima, Kozo Kimura, Hiroaki Hirata, Tokuzo Kiyohara, Shigeo Asahara, Takao Onoye, Isao Shirakawa:
Multi-Threaded Processor for Image Generation. 231-234 - Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen:
A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. 235-238 - Ping-Tsung Wang, Kun-Nen Chen, Yen-Tai Lai:
A High Performance FPGA with Hierarchical Interconnection Structure. 239-242 - Stephen P. S. Lam:
A 21/2-Dimensional Systolic Array Architecture. 243-246 - Shalini Yajnik, Niraj K. Jha:
Synthesis of Fault Tolerant Architectures for Molecular Dynamics. 247-250 - Philippe Duc, Didier Nicoulaz, Daniel Mlynek:
A RISC Controller with Customisation Facility for Flexible System Integration. 251-254 - Maini Williams, Jari Nurmi:
Multipurpose Chip for Physiological Measurements. 255-258
Architecture & Application II
- Nianxiong Tan, Sven Eriksson, Lars Wanhammar:
A Novel Bit-Serial Design of Comb Filters for Oversampling A/D Converters. 259-262 - Andrew G. Dempster, Malcolm D. Macleod:
Use of Multiplier Blocks to Reduce Filter Complexity. 263-266 - A. Tawfik, Fayez El Guibaly, Panajotis Agathoklis:
VLSI Array Processors Implementation of Block-State IIR Digital Filtentrs. 267-270 - Evaggelinos P. Mariatos, D. E. Metafas, John Ant. Hallas, Constantinos E. Goutis:
A Fast DCT Processor, Based on Special Purpose CORDIC Rotators. 271-274 - Erik De Man, Matthias Schöbinger, Tobias G. Noll, Georg Sebald:
A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators. 275-278
VLSI Circuits & Computational Theory
- C. T. Clark, Graham R. Nudd, Stephen Summerfield:
Current Mode Techniques for Multiple Valued Arithmetic and Logic. 279-282 - Marek J. Patyra, John E. Long:
Synthesis of Current Mode Building Blocks for Fuzzy Logic Control Circuits. 283-286 - Mark Bracey, William Redman-White, John B. Hughes:
A Switched-Current Sigma Delta Converter for Direct Photodiode Interfacing. 287-290 - Marc Renaudin, Bachar El-Hassan:
The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. 291-294 - Cheng-Wen Wu, Yung-Fa Chou:
General Modular Multiplication by Block Multiplication and Table Lookup. 295-298 - Jack L. Meador, Paul Hylander:
A Pulse Coded Winner-Take-All Circuit. 299-302 - D. Schin, Yinan N. Shen, Fabrizio Lombardi:
An Approach for UIO Generation for FSM Verification and Validation. 303-306 - Sebastian T. J. Fenn, David Taylor, Mohammed Benaissa:
A Dual Basis Systolic Divider for GF(2m). 307-310 - Hosahalli R. Srinivas, Keshab K. Parhi:
A Fast Radix-4 Division Algorithm. 311-314
(Posters): VLSI Circuits
- Weinan Gao, W. Martin Snelgrove:
Floating Gate Charge-Sharing: a Novel Circuit for Analog Trimming. 315-318 - Daejong Kim, Jaejin Park, Sungjoon Kim, Deog-Kyoon Jeong, Wonchan Kim:
A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter. 319-322 - James B. Kuo, K. W. Su, J. H. Lou:
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. 323-326 - Ali El-Zein, Monjurul Haque, Salim Chowdhury:
Simulating Nonuniform Lossy Lines with Frequency Dependent Parameters by the Method of Characteristics. 327-330 - Monjurul Haque, Ali El-Zein, Salim Chowdhury:
Transient Simulation of Nonuniform Transmission Lines by Asymptotic Waveform Evaluation. 331-334 - P. Zhou, J. C. Czilli, Graham A. Jullien, William C. Miller:
Current Input TSPC Latch for High Speed, Complex Switching Trees. 335-338 - Tobi Delbruck, Carver Mead:
Adaptive Photoreceptor with Wide Dynamic Range. 339-342 - Mohamed Nekili, Yvon Savaria, Guy Bois:
A Fast Low-Power Driver for Long Interconnections in VLSI Systems. 343-346 - Sameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria:
A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. 347-350 - Reza Golshan, Baher Haroun:
A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. 351-354 - Kei-Yong Khoo, Alan N. Willson Jr.:
Low Power CMOS Clock Buffer. 355-358 - Yvon Savaria, Dmitri Chtchvyrkov, John F. Currie:
A Fast CMOS Voltage-Controlled Ring Oscillator. 359-362 - Iulian B. Ciocoiu:
Circuit Implementation of a Nonmonotone Activation Function. 363-366
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