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ISCAS 2011: Rio de Janeiro, Brazil
- International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil. IEEE 2011, ISBN 978-1-4244-9473-6
Analog to Digital Converters I
- Long Cheng, Fan Ye, Hai-Feng Yang, Ning Li, Jun Xu, Junyan Ren:
Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching. 5-8 - Andrew R. Macpherson, Kenneth A. Townsend, James W. Haslett:
A 2.5GS/s 3-bit time-based ADC in 90nm CMOS. 9-12 - Pouya Kamalinejad, Shahriar Mirabbasi, Victor C. M. Leung
:
An ultra-low-power SAR ADC with an area-efficient DAC architecture. 13-16
Amplifiers
- Hitesh Shrimali, Shouri Chatterjee
:
11 GHz UGBW Op-amp with feed-forward compensation technique. 17-20 - James Lin
, Masaya Miyahara, Akira Matsuzawa:
A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. 21-24 - Davide Marano
, Gaetano Palumbo, Salvatore Pennisi
:
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications. 29-32 - Miao Liu, Pui-In Mak
, Zushu Yan, Rui Paulo Martins
:
A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies. 33-36
Low-Dropout Regulator
- S. S. Chong, P. K. Chan:
A quiescent power-aware low-voltage output capacitorless low dropout regulator for SoC applications. 37-40 - Stefano Pietri
, Chris Dao, Jehoda Refaeli, Alfredo Olmos, Xiaolei Wu:
A versatile low-dropout voltage regulator for automotive applications. 41-44 - Chenchang Zhan, Wing-Hung Ki
:
An output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction for SoC. 45-48 - Sumantra Seth, Rajavelu Thinakaran, Sujoy Chakravarty, Vikas Sinha:
A low power high speed envelope detector for serial data systems in 45nm CMOS. 49-52 - Edward N. Y. Ho, Philip K. T. Mok
:
Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique. 53-56
Memory Circuits I
- Gregory K. Chen, Michael Wieckowski, Daeyeon Kim, David T. Blaauw, Dennis Sylvester:
A dense 45nm half-differential SRAM with lower minimum operating voltage. 57-60 - Roghayeh Saeidi
, Mohammad Sharifkhani, Khosrow Hajsadeghi:
A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria. 61-64 - Farah B. Yahya, Mohammad M. Mansour, Ali Chehab
:
A novel technique to measure data retention voltage of large SRAM arrays. 65-68 - Daeyeon Kim, Gregory K. Chen, Matthew Fojtik, Mingoo Seok, David T. Blaauw, Dennis Sylvester:
A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme. 69-72 - Lawrence T. Clark, Tai-Hua Chen, Vikas Chaudhary:
Efficient voltage conversion for SRAM low standby power modes. 73-76
Life Science Systems & Applications
- Amit Acharyya
, Koushik Maharatna
, Bashir M. Al-Hashimi, Hasitha Tudugalle:
Simplified logic design methodology for fuzzy membership function based robust detection of maternal modulus maxima location: A low complexity Fetal ECG extraction architecture for mobile health monitoring systems. 77-80 - Alessander Botti Benevides, Teodiano Freire Bastos-Filho
, Mário Sarcinelli Filho
:
A pseudo-online Brain-Computer Interface with automatic choice for EEG channel and frequency. 81-84 - Michel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui:
Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction. 85-88 - Rafael José Geraldo, Nelson D. A. Mascarenhas:
Noise reduction filters based on pointwise MAP for CT images. 89-92 - Dan Wang, Xiang Xie, Guolin Li, Yingke Gu, Tianjia Sun, Zhihua Wang:
Image registration method for 2D representation of wireless Micro-Ball endoscopic images. 93-96
Image & Video Coding
- Lin Ma, Songnan Li, King N. Ngan:
Perceptual image compression via adaptive block- based super-resolution directed down-sampling. 97-100 - Zhaotai Pan, Huifeng Shen, Yan Lu, Shipeng Li
:
Browser-friendly hybrid codec for compound image compression. 101-104 - Xiulian Peng, Jizheng Xu, Feng Wu:
Highly parallel image coding for many cores. 105-108 - Je-Won Kang, C.-C. Jay Kuo
, Robert A. Cohen, Anthony Vetro:
Efficient dictionary based video coding with reduced side information. 109-112 - Run Cha, Oscar C. Au, Xingyu Zhang, Xing Wen, Jiali Li:
Multiple sub-pixel interpolation filters with adaptive symmetry for high-resolution video coding. 113-116
Adaptive Techniques in Signal and Image Processing Applications
- Shing-Chow Chan, Yijing Chu, Kai Man Tsui, Zhiguo Zhang:
A new switch-mode noise-constrained transform domain NLMS adaptive filtering algorithm. 117-120 - Pramod Kumar Meher, Megha Maheshwari:
A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm. 121-124 - Alexandre L. M. Levada
, Débora C. Corrêa:
An adaptive approach for contextual audio denoising using local Fisher information. 125-128 - Dinei A. F. Florêncio, Li-wei He:
Enhanced adaptive playout scheduling and loss concealment techniques for Voice over IP networks. 129-132 - Ariel L. Pola, Diego E. Crivelli, Juan E. Cousseau, Oscar E. Agazzi, Mario Rafael Hueda:
A new low complexity iterative equalization architecture for high-speed receivers on highly dispersive channels: Decision feedforward equalizer (DFFE). 133-136
FIR Digital Filters
- Mohammad Ahsan, Tapio Saramäki:
"A MATLAB based optimum multiband FIR filters design program following the original idea of the Remez multiple exchange algorithm". 137-140 - Ya Jun Yu:
Design of variable bandedge FIR filters with extremely large bandedge variation range. 141-144 - Wen Bin Ye, Ya Jun Yu:
Switching activity analysis and power estimation for multiple constant multiplier block of FIR filters. 145-148 - Alessandro J. S. Dutra, Lisandro Lovisolo
, Eduardo A. B. da Silva, Paulo S. R. Diniz
:
Successive approximation FIR filter design. 149-152
Digitally Intensive Frequency Synthesis Architectures for the Nano-Scale - Part I
- Ioannis L. Syllaios, Poras T. Balsara:
Multi-clock domain analysis and modeling of all-digital frequency synthesizers. 153-156 - David Ruffieux, Matteo Contaldo, Christian C. Enz:
MEMS-based all-digital frequency synthesis for ultralow-power radio for WBAN and WSN applications. 157-160 - Francesco Brandonisio, Michael Peter Kennedy:
First order noise shaping in all digital PLLs. 161-164 - Eric A. M. Klumperink, Ramen Dutta, Zhiyu Ru, Bram Nauta
, Xiang Gao:
Jitter-Power minimization of digital frequency synthesis architectures. 165-168 - Victor R. Gonzalez-Diaz, Aldo Pena-Perez, Franco Maloberti:
Use of time variant digital sigma-delta for fractional frequency synthesizers. 169-172
Wireline Communications I
- Shuai Chen, Liqiong Yang, Hua Jing, Feng Zhang, Zhuo Gao:
A novel SST transmitter with mutually decoupled impedance self-calibration and equalization. 173-176 - Soojin Kim, Kyeongsoon Cho:
Design of high-speed clock recovery circuit for burst-mode applications. 177-180 - Nguyen Thanh Trung, Philipp Häfliger
:
250Mb/s to 3Gb/s unilateral continuous rate CDR using precise frequency detector and 1/5-rate linear phase detector. 181-184 - Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu:
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. 185-188 - Marcello Ganzerli, Luca Larcher
, Simone Erba, Davide Sanzogni:
An inductor-less 13.5-Gbps 8-mW analog equalizer for multi-channel multi-frequency operation. 189-192
Advanced Transmitter Design Techniques
- Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty:
Slew-rate controlled 800Mbps transmitter in 65nm CMOS. 193-196 - Po-Hsing Wu, Yan Li, Weibo Hu, Jerry Lopez, Donald Y. C. Lie, T. J. Liang:
CMOS Envelope Tracking amplifier IC design for high-efficiency RF polar transmitters. 197-200 - Nagarjuna Nallam, Shouri Chatterjee
:
Design of concurrent multi-band matching networks. 201-204 - Imran Bashir, Robert Bogdan Staszewski
:
Autonomous predistortion calibration of an RF power amplifier. 205-208 - Sungmin Ock, Jaegan Ko, Ranjit Gharpurey:
A Cartesian Feedback Feedforward Transmitter. 209-212
Oscillators
- Fatemeh Aghlmand, Seyed Mojtaba Atarodi
, Saeed Saeedi
:
Low phase noise on-chip oscillator for implantable biomedical applications. 213-216 - Andrea Bevilacqua
, Pietro Andreani:
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory. 217-220 - Mauricio Pardo
, Logan Sorenson, Farrokh Ayazi:
A phase-noise model for nonlinear piezoelectrically-actuated MEMS oscillators. 221-224 - Li Lu, Changzhi Li
, Jenshan Lin
:
A regulated 3.1-10.6 GHz linear dual-tuning differential ring oscillator for UWB applications. 225-228 - Young-Seok Park, Woo-Young Choi:
Supply noise insensitive ring VCO with on-chip adaptive bias-current and voltage-swing control. 229-232
Power Converter I
- Ming Chak Lee, Xiaocheng Jing, Philip K. T. Mok
:
A 14V-output adaptive-off-time boost converter with quasi-fixed-frequency in full loading range. 233-236 - Chu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang
:
A high-efficiency PWM DC-DC buck converter with a novel DCM control under light-load. 237-240 - Dakshina Murthy-Bellur, Marian K. Kazimierczuk:
Active-clamp ZVS two-switch flyback converter. 241-244 - Yi Zhang, Dongsheng Ma:
Integrated SIMO DC-DC converter with on-line charge meter for adaptive PCCM operation. 245-248 - Moises Tanca V., Ivo Barbi
:
Nonisolated high step-up stacked dc-dc converter based on boost converter elements for high power application. 249-252
Analog to Digital Converters II
- Ji-Eun Jang:
Comparator-based switched-capacitor pipelined ADC with background offset calibration. 253-256 - Yu Lin, Kostas Doris, Hans Hegt, Arthur H. M. van Roermund:
An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals. 257-260 - Taimur Gibran R. Kuntz
, Cesar Ramos Rodrigues
, Saeid Nooshabadi:
An energy-efficient 1MSps 7µW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm. 261-264 - Andrew J. Bean, Andrew C. Singer
:
A deflection criterion for time-interleaved analog-to-digital converters. 265-268 - Jingbo Duan, Degang Chen:
SNR measurement based on linearity test for ADC BIST. 269-272
Low-Noise Amplifiers
- Edwin C. Becerra-Alvarez, José M. de la Rosa, Federico Sandoval-Ibarra:
Design considerations and experimental results of continuously-tuned reconfigurable CMOS LNAs. 273-276 - Mohammad Sadegh Mehrjoo, Mohammad Yavari
:
A low power UWB very low noise amplifier using an improved noise reduction technique. 277-280 - Md. Mahbub Reja, Igor M. Filanovsky
, Kambiz K. Moez:
A compact CMOS UWB LNA using tunable active inductors for WLAN interference rejection. 281-284 - Shreyas Sen, Marian Verhelst
, Abhijit Chatterjee:
Orthogonally tunable inductorless RF LNA for adaptive wireless systems. 285-288 - Miguel A. Martins, Pui-In Mak
, Rui Paulo Martins
:
A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance. 289-292
Emerging Energy & Power Integrated Circuits
- Jing Wang, Wai Tung Ng, Olivier Trescases:
Versatile capabilities of digitally controlled integrated dc-dc converters. 293-296 - Xiaocheng Jing, Philip K. T. Mok
:
Ultra-fast hysteretic single-inductor-dual-output boost regulator with predictable noise spectrum and minimized cross-regulation. 297-300 - Eduard Alarcón, Daniel Fernández
, Albert Garcia-Tormo, Jordi Madrenas
, Alberto Poveda:
Continuous-time CMOS adaptive asynchronous ΣΔ modulator approximating low-ƒs low-inband-error on-chip wideband power amplifier. 301-304 - Ka Nang Leung
, Marco Ho
, Jianping Guo, Pui Ying Or:
Development of energy-efficient fast-transient CMOS low-dropout regulators for SoC applications. 305-308 - Rajiv Damodaran Prabha, Gabriel A. Rincón-Mora, Suhwan Kim:
Harvesting circuits for miniaturized photovoltaic cells. 309-312
Memory Circuits II
- Jinyeong Moon
, Hye-young Lee:
A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs. 313-316 - Jinyeong Moon
, Joong Sik Kih:
Fast parallel CRC & DBI calculation for high-speed memories: GDDR5 and DDR4. 317-320 - Sangho Shin, Kyungmin Kim, Sung-Mo Kang:
Complementary structure of memristive devices based passive memory arrays. 321-324 - Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee
, Joseph Sylvester Chang:
A low-power dual-rail inputs write method for bit-interleaved memory cells. 325-328 - Nikolaos Papandreou, Haralampos Pozidis, Aggeliki Pantazi
, Abu Sebastian
, Matthew J. Breitwisch, Chung Hon Lam, Evangelos Eleftheriou:
Programming algorithms for multilevel phase-change memory. 329-332
Experiences with CAS teaching
- Jerzy Rutkowski, Katarzyna Moscinska:
Blended engineering course - Electric Circuit Theory case study. 333-336 - Eugene Otoakhia, Tanaporn Jenmanachaiyakun, Ahmad Afaneh
, Said Alzebda, Mohammad Mani, Omar S. Sonbul
, Alexander N. Kalashnikov:
Embedded web server for remote laboratory access for undergraduate students studying electronic engineering. 337-340 - Jan Kyncl, Martin Novotný
:
Education of Digital and Analog Circuits supported by computer algebra system. 341-344 - Jordi Albo-Canals, Giovanni Egidio Pazienza:
How to teach memristors in EE undergraduate courses. 345-348 - Joos Vandewalle, Josef A. Nossek
:
Nullators and norators in circuits education: A benefit or an obstacle? 349-352
Visual Signal Analysis & Understanding
- Jingjing Fan, Yanzhe Xin, Fenglin Dai, Bo Hu, Jianqiu Zhang, Qiyong Lu, Jun He:
Distributed multi-camera object tracking with Bayesian Inference. 357-360 - Hongyu Gao, Weiyao Lin
, Xiaokang Yang, Hongxiang Li, Ning Xu, Jun Xie, Yan Li:
A new network-based algorithm for multi-camera abnormal activity detection. 361-364 - Zhebin Zhang, Yizhou Wang, Tingting Jiang
, Wen Gao:
Stereoscopic learning for disparity estimation. 365-368
Detection and Estimation
- Luis Weruaga, O. Michael Melko:
On the Cramér-Rao bound of autoregressive estimation in noise. 373-376 - Bin Liao
, Shing-Chow Chan:
DOA estimation of coherent signals for uniform linear arrays with mutual coupling. 377-380 - Diego Bellan
:
An improved model of jitter effects in analog-to-digital conversion. 381-384 - Ahmed Abdelgawad, Magdy A. Bayoumi:
Distributed Kalman Filter using fast polynomial filter. 385-389 - Jian-Feng Gu, Wei-Ping Zhu
, M. N. S. Swamy:
Minimum redundancy linear sparse subarrays for direction of arrival estimation without ambiguity. 390-393
Digital Filter Design & Implementation
- Soo-Chang Pei, Jong-Jy Shyu, Cheng-Han Chan, Yun-Da Huang:
An Improved method for the design of variable fractional-delay IIR digital filters. 394-397 - Wu-Sheng Lu, Takao Hinamoto:
Minimax design of stable IIR filters with sparse coefficients. 398-401 - Bashar I. Ahmad, Andrzej Tarczynski
:
A spectrum sensing method based on stratified sampling. 402-405 - Yu Pan, Pramod Kumar Meher:
Efficient coefficient partitioning for decomposed DA-based inner-product computation. 406-409 - Dieter Brückmann, Tobias Feldengut, Bedrich J. Hosticka, Rainer Kokozinski
, Karsten Konrad, Nima Tavangaran:
Optimization and implementation of continuous time DSP-systems by using granularity reduction. 410-413
Digitally Intensive Frequency Synthesis Architectures for the Nano-Scale - Part II
- Ulrich L. Rohde, Ajay K. Poddar:
Digital frequency synthesizer using adaptive mode-coupled resonator mechanism for low phase noise and low jitter applications. 414-417 - Carlo Samori
, Marco Zanuso, Salvatore Levantino
, Andrea L. Lacaita
:
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. 418-421 - Paul-Peter Sotiriadis
:
Spurs suppression and deterministic jitter correction in all-digital frequency synthesizers, current state and future directions. 422-425 - Robert Bogdan Staszewski
:
All-digital RF frequency modulation. 426-429
Wireline Communications II
- Won-Young Lee, Lee-Sup Kim:
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation. 430-433 - Chua-Chin Wang, Chih-Lin Chen, Tai-Hao Yeh, Yi Hu, Gang-Neng Sung:
A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems. 434-437 - Jea Hack Lee
, Myung Hoon Sunwoo:
High-speed and low complexity carrier recovery for DP-QPSK transmission. 438-441 - Yin-Tsung Hwang, Feng-Ming Chang, Shin-Wen Chen:
Low complexity baseband transceiver design for narrow band power line communication. 442-445 - Arash Zargaran-Yazd, Shahriar Mirabbasi, Res Saleh:
A 10 Gb/s low-power serdes receiver based on a hybrid speculative/SAR digitization technique. 446-449
Advanced Baseband Design Techniques
- Sandeep D'Souza, Mau-Chung Frank Chang, Sudhakar Pamarti
, Bipul Agarwal, Hossein Zarei, Tirdad Sowlati, Roc Berenguer
:
A progammable baseband anti-alias filter for a passive-mixer-based, SAW-less, multi-band, multi-mode WEDGE transmitter. 450-453 - Fernando Cruz-Roldán, Manuel Blanco-Velasco
, Juan Ignacio Godino-Llorente
:
MDFT filter bank multicarrier systems with multiple transmission zeros. 454-457 - Mohamed Mohi, Ahmed F. Shalash:
All digital time tracking loop for DVB-H and DVB-T. 458-461 - Yizhi Wang, Yun Chen, Yunlong Ge, Huxiong Xu, Xiaoyang Zeng:
A channel estimation scheme for Chinese DTTB system combating long echo and high doppler shift. 462-465 - Johan Löfgren, Ove Edfors
, Peter Nilsson:
Improved matching pursuit algorithm and architecture for LTE Channel Estimation. 466-469
PLL
- Mauricio Pardo
, Farrokh Ayazi:
A band-reject nested-PLL phase-noise reduction scheme for clock-cleaners. 470-473 - Zhuo Zhang, Woogeun Rhee
, Zhihua Wang:
A wide-tuning quasi-type-I PLL with voltage-mode frequency acquisition aid. 474-477 - Xiaoming Liu, Jing Jin, Xi Li, Jianjun Zhou
:
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs. 478-481 - P. O. Lucas de Peslouan, Cédric Majek, Thierry Taris, Yann Deval
, Didier Belot, Jean-Baptiste Bégueret:
A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture. 482-485 - Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo:
All digital phase-locked loop using active inductor oscillator and novel locking algorithm. 486-489
Power Converter II
- Masato Asano, Daiki Abe, Hirotaka Koizumi:
A common grounded Z-source buck-boost converter. 490-493 - Younis Allasasmeh, Stefano Gregori
:
Switch bootstrapping technique for voltage doublers and double charge pumps. 494-497 - Yu-Sheng Chen
, Tsorng-Juu Liang, Kai-Hui Chen, Jer-Nan Juang:
Study and implementation of high frequency pulse LED driver with self-oscillating circuit. 498-501 - Franz Lukasch:
Cost efficient mains powered supply concepts for wireless sensor nodes. 502-505