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ISSCC 2020: San Francisco, CA, USA
- 2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020. IEEE 2020, ISBN 978-1-7281-3205-1
- Sensen Li, Taiyun Chi, Doohwan Jung, Tzu-Yuan Huang, Min-Yu Huang, Hua Wang:
4.2 An E-Band High-Linearity Antenna-LNA Front-End with 4.8dB NF and 2.2dBm IIP3 Exploiting Multi-Feed On-Antenna Noise-Canceling and Gm-Boosting. 1-3 - Moon Hyung Jang, Changuk Lee, Youngcheol Chae:
9.2 A 134µW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC. 1-3 - Jeffrey Dean:
1.1 The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design. 8-14 - Kou-Hung Lawrence Loh:
1.2 Fertilizing AIoT from Roots to Leaves. 15-21 - Nadine Collaert:
1.3 Future Scaling: Where Systems and Technology Meet. 25-29 - Dario Gil, William M. J. Green:
1.4 The Future of Computing: Bits + Neurons + Qubits. 30-39 - Teja Singh, Sundar Rangarajan, Deepesh John, Russell Schreiber, Spence Oliver, Rajit Seahra, Alex Schaefer:
2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core. 42-44 - Samuel Naffziger, Kevin Lepak, Milam Paraschou, Mahesh Subramony:
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 44-45 - Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. 46-48 - Young-Duk Kim, Wookyeong Jeong, Lakkyung Jung, Dongsuk Shin, Jae Geun Song, Jinook Song, Hyeokman Kwon, Jaeyoung Lee, Jaesu Jung, Myungjin Kang, Jaehun Jeong, Yoonjoo Kwon, Nak Hee Seong:
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU. 48-50 - Hugh Mair, Ericbill Wang, Ashish Nayak, Rolf Lagerquist, Loda Chou, Gordon Gammie, HsinChen Chen, Lee-Kee Yong, Manzur Rahman, Jenny Wiedemeier, Ramu Madhavaram, Alex Chiou, Blundt Li, Vincent Lin, Rory Huang, Michael Yanq, Achuta Thippana, Osric Su, S. A. Huang:
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC. 50-52 - Rama Venkatasubramanian, Don Steiss, Greg Shurtz, Tim Anderson, Kai Chirca, Raghavendra Santhanagopal, Niraj Nandan, Anish Reghunath, Hetul Sanghvi, Daniel Wu, Abhijeet Chachad, Brian Karguth, Denis Beaudoin, Charles Fuoco, Lewis Nardini, Chunhua Hu, Sam Visalli, Amrit Mundra, Devanathan Varadarajan, Frank Cano, Shane Stelmach, Mihir Mody, Arthur Redfern, Haydar Bilhan, Maher Sarraj, Ali Siddiki, Anthony Lell, Eldad Falik, Anthony M. Hill, Abhinay Armstrong, Todd Beck, Vijay Kanumuri, Steven Mullinnix, Darnell Moore, Jason Jones, Manoj Koul, Sanjive Agarwala:
2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. 52-54 - Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Pradeep Parashurama, Ramon Bertran, Dureseti Chidambarrao, David Wolpert, Brandon Bruen:
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor. 54-56 - Danielle Griffith, Ernest Ting-Ta Yen, Kaichien Tsai, Habeeb Ur Rahman Mohammed, Baher Haroun, Ali Kiaei, Ahmad Bahai:
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production. 58-60 - Amr Khashaba, Junheng Zhu, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
3.2 A 0.0088mm2 Resistor-Based Temperature Sensor Achieving 92fJ·K2 FoM in 65nm CMOS. 60-62 - Li Xu, Tae-Kwang Jang, Jongyup Lim, Kyojin David Choo, David T. Blaauw, Dennis Sylvester:
3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection. 62-64 - Çagri Gürleyük, Sining Pan, Kofi A. A. Makinwa:
3.4 A 16MHz CMOS RC Frequency Reference with ±400ppm Inaccuracy from -45°C to 85°C After Digital Linear Temperature Compensation. 64-66 - Amr Khashaba, Junheng Zhu, Mostafa Gamal Ahmed, Nilanjan Pal, Pavan Kumar Hanumolu:
3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors. 66-68 - Sining Pan, Kofi A. A. Makinwa:
3.6 A CMOS Resistor-Based Temperature Sensor with a 10fJ·K2 Resolution FoM and 0.4°C (30) Inaccuracy From -55°C to 125°C After a 1-point Trim. 68-70 - Saleh Heidary Shalmany, Kamran Souri, Uaur Sonmez, Kianoush Souri, Michele D'Urbino, Said Hussaini, Darryl Tauro, Sassan Tabatabaei:
3.7 A 620µW BJT-Based Temperature-to-Digital Converter with 0.65mK Resolution and FoM of 190fJ·K2. 70-72 - Chenu-Hsing Liao, Shang-Hsien Yang, Meng-Yin Liao, Kai-Cheng Chung, Neha Kumari, Ke-Horng Chen, Yin-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Ying-Zong Juang:
3.8 A 23.6ppm/°C Monolithically Integrated GaN Reference Voltage Design with Temperature Range from -50°C to 200°C and Supply Voltage Range from 3.9 to 24V. 72-74 - Hyun-Chul Park, D. Kang, S. M. Lee, B. Park, K. Kim, Jooseok Lee, Y. Aoki, Y. Yoon, S. Lee, D. Lee, D. Kwon, Seokhyeon Kim, J. Kim, W. Lee, C. Kim, S. Park, J. Park, B. Suh, J. Jang, M. Kim, Donggyu Minn, I. Park, S. Kim, K. Min, S. Jeon, A.-S. Ryu, Y. Cho, S. T. Choi, K. H. An, Y. Kim, J. H. Lee, Jae-Ick Son, Sung-Gi Yang:
4.1 A 39GHz-Band CMOS 16-Channel Phased-Array Transceiver IC with a Companion Dual-Stream IF Transceiver IC for 5G NR Base-Station Applications. 76-78 - Robin Garg, Gaurav Sharma, Ali Binaie, Sanket Jain, Sohail Ahasan, Armagan Dascurcu, Harish Krishnaswamy, Arun Natarajan:
4.3 A 28GHz 4-Element MIMO Beam-Space Array in 65nm CMOS with Simultaneous Spatial Filtering and Single-Wire Frequency-Domain Multiplexing. 80-82 - Susnata Mondal, L. Richard Carley, Jeyanandh Paramesh:
4.4 A 28/37GHz Scalable, Reconfigurable Multi-Layer Hybrid/Digital MIMO Transceiver for TDD/FDD and Full-Duplex Communication. 82-84 - Anandaroop Chakrabarti, Chintan Thakkar, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper:
4.5 A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance. 84-86 - Xuyang Lu, Suresh Venkatesh, Bingjun Tang, Kaushik Sengupta:
4.6 Space-Time Modulated 71-to-76GHz mm-Wave Transmitter Array for Physically Secure Directional Wireless Links. 86-88 - Milad Kalantari, Hossein Shirinabadi, Ali Fotowat-Ahmadi, C. Patrick Yue:
4.7 A Single-Antenna W-Band FMCW Radar Front-End Utilizing Adaptive Leakage Cancellation. 88-90 - Xiang Yi, Cheng Wang, Muting Lu, Jinchen Wang, Jesús Grajal, Ruonan Han:
4.8 A Terahertz FMCW Comb Radar in 65nm CMOS with 100GHz Bandwidth. 90-92 - Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka, Katsuyuki Kimura, Akihide Sai, Nobu Matsumoto:
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE. 94-96 - Toru Okino, Shota Yamada, Yusuke Sakata, Shigetaka Kasuga, Masato Takemoto, Yugo Nose, Hiroshi Koshida, Masaki Tamaru, Yuki Sugiura, Shigeru Saito, Shinzo Koyama, Mitsuyoshi Mori, Yutaka Hirose, Masayuki Sawada, Akihiro Odagawa, Tsuyoshi Tanaka:
5.2 A 1200×900 6µm 450fps Geiger-Mode Vertical Avalanche Photodiodes CMOS Image Sensor for a 250m Time-of-Flight Ranging System Using Direct-Indirect-Mixed Frame Synthesis with Configurable-Depth-Resolution Down to 10cm. 96-98 - C.-L. Chen, S.-W. Chu, B.-J. Chen, Y.-F. Lyu, Kai-Chi Hsu, C.-F. Liang, S.-S. Su, M.-J. Yang, C.-Y. Chen, S.-L. Cheng, H.-D. Liu, C.-T. Lin, K. P. Petrov, H.-W. Chen, K.-C. Chu, P.-C. Wu, P.-T. Huang, Neil Na, S.-L. Chen:
5.3 An Up-to-1400nm 500MHz Demodulated Time-of-Flight Image Sensor on a Ge-on-Si Platform. 98-100 - Donguk Kim, Seunghyun Lee, Dahwan Park, Canxing Piao, Jihoon Park, Yeonsoo Ahn, Kihwan Cho, Jungsoon Shin, Seung Min Song, Seong-Jin Kim, Jung-Hoon Chun, Jaehyuk Choi:
5.4 A Dynamic Pseudo 4-Tap CMOS Time-of-Flight Image Sensor with Motion Artifact Suppression and Background Light Cancelling Over 120klux. 100-102 - Jaekyu Lee, Seung Sik Kim, In-Gyu Baek, Heesung Shim, Taehoon Kim, Taehyoung Kim, Jungchan Kyoung, Dongmo Im, Jinyong Choi, KeunYeong Cho, Daehoon Kim, Haemin Lim, Min-Woong Seo, JuYoung Kim, Doowon Kwon, Jiyoun Song, Jiyoon Kim, Minho Jang, Joosung Moon, Hyunchul Kim, Chong Kwang Chang, JinGyun Kim, Kyoungmin Koh, Hanjin Lim, JungChak Ahn, Hyeongsun Hong, Kyupil Lee, Ho-Kyu Kang:
5.5 A 2.1e- Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology. 102-104 - Hyunchul Kim, Jongeun Park, Insung Joe, Doowon Kwon, Joo Hyoung Kim, Dongsuk Cho, Taehun Lee, Changkyu Lee, Haeyong Park, Soojin Hong, Chongkwang Chang, Jingyun Kim, Hanjin Lim, Youngsun Oh, Yitae Kim, Seungjoo Nah, Sangil Jung, Jaekyu Lee, JungChak Ahn, Hyeongsun Hong, Kyupil Lee, Ho-Kyu Kang:
5.6 A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology. 104-106 - Yorito Sakano, Takahiro Toyoshima, Ryosuke Nakamura, Tomohiko Asatsuma, Yuki Hattori, Takayuki Yamanaka, Ryoichi Yoshikawa, Naoki Kawazu, Tomohiro Matsuura, Takahiro Iinuma, Takahiro Toya, Tomohiko Watanabe, Atsushi Suzuki, Yuichi Motohashi, Junichiro Azami, Yasushi Tateshita, Tsutomu Haruta:
5.7 A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance. 106-108 - Mamoru Sato, Yuhi Yorikado, Yusuke Matsumura, Hideki Naganuma, Eriko Kato, Takuya Toyofuku, Akihiko Kato, Yusuke Oike:
5.8 A 0.50e-rmsNoise 1.45µm-Pitch CMOS Image Sensor with Reference-Shared In-Pixel Differential Amplifier at 8.3Mpixel 35fps. 108-110 - Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh:
5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel. 110-112 - Thomas Finateu, Atsumi Niwa, Daniel Matolin, Koya Tsuchimoto, Andrea Mascheroni, Etienne Reynaud, Pooria Mostafalu, Frederick T. Brady, Ludovic Chotard, Florian Le Goff, Hirotsugu Takahashi, Hayato Wakabayashi, Yusuke Oike, Christoph Posch:
5.10 A 1280×720 Back-Illuminated Stacked Temporal Contrast Event-Based Vision Sensor with 4.86µm Pixels, 1.066GEPS Readout, Programmable Event-Rate Controller and Compressive Data-Formatting Pipeline. 112-114 - Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Ahn, Hongtao Zhang, Yohan Frans, Ken Chang:
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. 116-118 - Tamer A. Ali, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung:
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. 118-120 - Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Nhat Nguyen, Shaishav Desai:
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET. 120-122 - Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin:
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. 122-124 - Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong:
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. 124-126 - Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. 126-128 - Han-Gon Ko, Soyeong Shin, Jonghyun Oh, Kwanseo Park, Deog-Kyoon Jeong:
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. 128-130 - Pen-Jui Peng, Sheng-Tsung Lai, Wei-Hung Wang, Chiang-Wei Lin, Wei-Chien Huang, Ted Shih:
6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS. 130-132 - Chien-Hung Lin, Chih-Chung Cheng, Yi-Min Tsai, Sheng-Je Hung, Yu-Ting Kuo, Perry H. Wang, Pei-Kuei Tsung, Jeng-Yun Hsu, Wei-Chih Lai, Chia-Hung Liu, Shao-Yu Wang, Chin-Hua Kuo, Chih-Yu Chang, Ming-Hsien Lee, Tsung-Yao Lin, Chih-Cheng Chen:
7.1 A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC. 134-136 - Yang Jiao, Liang Han, Rong Jin, Yi-Jung Su, Chiente Ho, Li Yin, Yun Li, Long Chen, Zhen Chen, Lu Liu, Zhuyu He, Yu Yan, Jun He, Jun Mao, Xiaotao Zai, Xuejun Wu, Yongquan Zhou, Mingqiu Gu, Guocai Zhu, Rong Zhong, Wenyuan Lee, Ping Chen, Yiping Chen, Weiliang Li, Deyu Xiao, Qing Yan, Mingyuan Zhuang, Jiejun Chen, Yun Tian, Yingzi Lin, Wei Wu, Hao Li, Zesheng Dou:
7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS. 136-140 - Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura:
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. 138-140 - Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo:
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation. 140-142 - Wilfred Gomes, Sanjeev Khushu, Doug B. Ingerly, Patrick N. Stover, Nasirul I. Chowdhury, Frank O'Mahony, Ajay Balankutty, Noam Dolev, Martin G. Dixon, Lei Jiang, Surya Prekke, Biswajit Patra, Pavel V. Rott, Rajesh Kumar:
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm2, 1mm Package-on-Package. 144-146 - Prasun K. Raha, Tomai Knopp, Sagheer Ahmad, Ahmad Ansari, Fu-Hing Ho, Thomas To, Vamsi Nalluri, Mrinal Sarmah, Rajeev Patwari:
8.2 A Versatile 7nm Adaptive Compute Acceleration Platform Processor. 146-148 - Robert Christy, Stuart Riches, Sujil Kottekkat, Prasanth Gopinath, Ketan Sawant, Anitha Kona, Rob Harrison:
8.3 A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications. 148-150 - Sal Dasgupta, Teja Singh, Ashish Jain, Samuel Naffziger, Deepesh John, Chetan Bisht, Pradeep Jayaraman:
8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs. 150-152 - Su-Hao Wu, Yun-Shiang Shu, Albert Yen-Chih Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh:
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s. 154-156 - Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun:
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. 158-160 - Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn:
9.4 A 4th-Order Cascaded-Noise-Shaping SAR ADC with 88dB SNDR Over 100kHz Bandwidth. 160-162 - Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. 162-164 - Yan Song, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration. 164-166 - Mitsuya Fukazawa, Takashi Oshima, Masaki Fujiwara, Katsuki Tateyama, Alsubaie Raed, Masao Ito, Tetsuya Matsumoto, Tetsuo Matsui:
9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS. 166-168 - Robert H. M. van Veldhoven, Marco Lammers, Leon van der Dussen, Khalid Mabtoul:
9.8 A Low-Cost 4-Channel Reconfigurable Audio Interface for Car Entertainment Systems. 168-170 - Gengzhen Qi, Haijun Shao, Pui-In Mak, Jun Yin, Rui Paulo Martins:
10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise. 172-174 - Shiyu Su, Mike Shuo-Wei Chen:
10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. 174-176 - Ming-Da Tsai, Song-Yu Yang, Chi-Yao Yu, Ping-Yu Chen, Tzung-Han Wu, Mohammed Hassan, Chi-Tsan Chen, Chao-Wei Wang, Yen-Chuan Huang, Li-Han Hung, Wei-Hao Chiu, Anson Lin, Bo-Yu Lin, Arnaud Werquin, Chien-Cheng Lin, Yen-Horng Chen, Jen-Che Tsai, Yuan-Yu Fu, Bernard Tenbroek, Chinq-Shiun Chiu, Yi-Bin Lee, Guang-Kaai Dehng:
10.3 A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO. 176-178 - Eric Lu, Wen-Kai Li, Zhiming Deng, Edris Rostami, Pi-An Wu, Keng-Meng Chang, Yu-Chen Chuang, Chang-Ming Lai, Yang-Chuan Chen, Tzu-Hsuin Peng, Tzung-Chuen Tsai, Hui-Hsien Liu, Chien-Chih Chiu, Bryan Huang, Yao-Chi Wang, Jing-Hong Conan Zhan, Osama Shana'a:
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS. 178-180 - Assaf Ben Bassat, Shahar Gross, Anna Nazimov, Ashoke Ravi, Bassam Khamaisi, Elan Banin, Eli Borokhovich, Nahum Kimiagarov, Phillip Skliar, Rotem Banin, Sarit Zur, Sebastian Reinhold, Smadar Bruker, Tzvi Maimon, Uri Parker, Ofir Degani:
10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications. 180-182 - Ming-Da Tsai, Chien-Wei Tseng, Kuen-Jou Tsai, Shuja Andrabi, Pin-Cheng Huang, Federico Beffa, Yangjian Chen, Bernard Tenbroek:
10.6 A 4G/5G Cellular Transmitter in 12nm FinFET with Harmonic Rejection. 182-184 - Si-Wook Yoo, Shih-Chang Hung, Jeffrey S. Walling, David J. Allstot, Sang-Min Yoo:
10.7 A 0.26mm2 DPD-Less Quadrature Digital Transmitter With 30dB Pout Range in 65nm CMOS. 184-186 - Erfan Ghaderi, Chase Puglisi, Shrestha Bansal, Subhanshu Gupta:
10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS. 186-188 - Kang Wei, Yogesh Ramadass, Dongsheng Brian Ma:
11.1 A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation. 190-192 - Prescott H. McLaughlin, Ziyu Xia, Jason T. Stauth:
11.2 A Fully Integrated Resonant Switched-Capacitor Converter with 85.5% Efficiency at 0.47W Using On-Chip Dual-Phase Merged-LC Resonator. 192-194 - Christoph Rindfleisch, Bernhard Wicht:
11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency. 194-196 - Qi Cheng, Lin Cong, Hoi Lee:
11.4 A 48-to-80V Input 2MHz Adaptive ZVT-Assisted GaN-Based Bus Converter Achieving 14% Light-Load Efficiency Improvement. 196-198 - Mo Huang, Yan Lu, Rui Paulo Martins:
11.5 A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5. 198-200 - Sung-Wan Hong:
11.6 A 1.46mm2 Simultaneous Energy-Transferring Single-Inductor Bipolar-Output Converter with a Flying Capacitor for Highly Efficient AMOLED Display in 0.5µm CMOS. 200-202 - Jongbeom Baek, Takahiro Nomiyama, Seungchan Park, Young-Ho Jung, Dongsu Kim, Jae-Yeol Han, Jun-Suk Bang, Yumi Lee, Ik-Hwan Kim, Ji-Seon Paek, Jongwoo Lee, Thomas Byunghak Cho:
11.7 A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate. 202-204 - Min-Woo Ko, Gyeong-Gu Kang, Ki-Duk Kim, Ji-Hun Lee, Seok-Tae Koh, Tae-Hwang Kong, Sang-Ho Kim, Sungyong Lee, Michael Choi, Jongshin Shin, Gyu-Hyeong Cho, Hyunsik Kim:
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries. 204-206 - Hao Li, Ganesh Balamurugan, Meer Sakib, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James E. Jaussi, Bryan Casper:
12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control. 208-210 - Enrico Sentieri, Tino Copani, Andrea Paganini, Matteo Traldi, Angelo Palladino, Antonio Santipo, Lorenzo Gerosa, Matteo Repossi, Gianluca Catrini, Marta Campo, Francesco Radice, Andrea Diodato, Roberto Pelleriti, Daniele Baldi, Laura Tarantini, Luca Maggi, Gianluca Radaelli, Stefano Cervini, Francesco Clerici, Angelo Moroni:
12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications. 210-212 - Teruo Jyo, Munehiko Nagatani, Josuke Ozaki, Mitsuteru Ishikawa, Hideyuki Nosaka:
12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters. 212-214 - Hannes Ramon, Michiel Verplaetse, Michael Vanhoecke, Haolin Li, Johan Bauwelinck, Peter Ossieur, Xin Yin, Guy Torfs:
12.4 A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver. 214-216 - Doo-Hyun Kim, Hyunggon Kim, Sung-Won Yun, Youngsun Song, Jisu Kim, Sung-Min Joe, Kyung-Hwa Kang, Joonsuc Jang, Hyun-Jun Yoon, Kangbin Lee, Minseok Kim, Joonsoo Kwon, Jonghoo Jo, Sehwan Park, Jiyoon Park, Jisoo Cho, Sohyun Park, Garam Kim, Jinbae Bang, Heejin Kim, Jongeun Park, Deokwoo Lee, Seonyong Lee, Hwajun Jang, Hanjun Lee, Donghyun Shin, Jungmin Park, Jungkwan Kim, Jongmin Kim, Kichang Jang, II Han Park, Seung Hyun Moon, Myung-Hoon Choi, Pansuk Kwak, Joo-Yong Park, Youngdon Choi, Sanglok Kim, Seungjae Lee, Dongku Kang, Jeong-Don Lim, Dae-Seok Byeon, Ki-Whan Song, Jung-Hwan Choi, Sangjoon Hwang, Jaeheon Jeong:
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate. 218-220 - Hwang Huh, Wanik Cho, Jinhaeng Lee, Yujong Noh, Yongsoon Park, Sunghwa Ok, Jongwoo Kim, Kayoung Cho, Hyunchul Lee, Geonu Kim, Kangwoo Park, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Chankeun Kwon, Hanna Cho, Chanhui Jeong, Yujin Yang, Jayoon Goo, Jangwon Park, Juhyeong Lee, Heonki Kirr, Kangwook Jo, Cheoljoong Park, Hyeonsu Nam, Hyunseok Song, Sangkyu Lee, Woopyo Jeong, Kun-Ok Ahn, Tae-Sung Jung:
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique. 220-221 - Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Chieh-Pu Lo, Meng-Chun Shih, Kuei-Hung Shen, Harry Chuang, Tsung-Yung Jonathan Chang:
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference. 222-224 - Tung-Cheng Chang, Yen-Cheng Chiu, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Meng-Fan Chang:
13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices. 224-226 - Toshiyuki Kouchi, Noriyasu Kumazaki, Masashi Yamaoka, Sanad Bushnaq, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Akio Sugahara, Akihiro Imamoto, Norichika Asaoka, Ryosuke Isomura, Takaya Handa, Junichi Sato, Hiromitsu Komai, Atsushi Okuyama, Naoaki Kanagawa, Yasufumi Kajiyama, Yuri Terada, Hidekazu Ohnishi, Hiroki Yabe, Cynthia Hsu, Mami Kakoi, Masahiro Yoshihara:
13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs. 226-228 - Weiwei Shan, Minhao Yang, Jiaming Xu, Yicheng Lu, Shuai Zhang, Tao Wang, Jun Yang, Longxing Shi, Mingoo Seok:
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS. 230-232 - Zhe Yuan, Yixiong Yang, Jinshan Yue, Ruoyang Liu, Xiaoyu Feng, Zhiting Lin, Xiulong Wu, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. 232-234 - Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu:
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. 234-236 - Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li:
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. 238-240 - Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang:
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. 240-242 - Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. 242-244 - Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. 244-246 - Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang:
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. 246-248 - Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Bardsley, Christopher Dillon, Mohit Kumar, Matthew McShea, Ryan Bunch, Joel Prabhakar, Scott Puckett:
16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration. 250-252 - Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. 252-254 - Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. 254-256