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ORCIDISSoC 2012: Tampere, Finland
- 2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012. IEEE 2012, ISBN 978-1-4673-2895-1
- Saleh Abdel-Hafeez, Mohammad Shatnawi
, Ann Gordon-Ross:
A double data rate 8T-cell SRAM architecture for systems-on-chip. 1-4 - Roman Plyaskin, Thomas Wild, Andreas Herkersdorf:
System-level software performance simulation considering out-of-order processor execution. 1-7 - Jeroen Declerck, Prabhat Avasare, Miguel Glassee, Amir Amin, Erik Umans, Andy Dewilde, Praveen Raghavan, Martin Palkovic:
A flexible platform architecture for Gbps wireless communication. 1-6 - Abdul Naeem, Axel Jantsch, Zhonghai Lu:
Scalability analysis of release and sequential consistency models in NoC based multicore systems. 1-7 - Liang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen:
Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs. 1-7 - Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Application-aware spinlock control using a hardware scheduler in MPSoC platforms. 1-6 - Di Wu, Junwhan Ahn, Imyong Lee, Kiyoung Choi:
Resource-shared custom instruction generation under performance/area constraints. 1-6 - Antonio Miele, Christian Pilato, Donatella Sciuto:
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs. 1-6 - Martin Broich, Tobias G. Noll:
Efficient VLSI architectures of QPP interleavers for LTE turbo decoders. 1-6 - Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler:
CRAVE: An advanced constrained random verification environment for SystemC. 1-7 - Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Fernando Gehm Moraes, Manfred Glesner:
Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs. 1-4 - Anthony Van Herrewege, Ingrid Verbauwhede:
Tiny application-specific programmable processor for BCH decoding. 1-4 - Ling Wang, Zhen Wang, Yingtao Jiang:
A hybrid chip interconnection architecture with a global wireless network overlaid on top of a wired network-on-chip. 1-4 - Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme:
Statistical timing characterization. 1-4 - Ilya Chukhman, William Plishker, Shuvra S. Bhattacharyya:
Instrumentation-driven model detection for dataflow graphs. 1-8 - Mohammad Reza Kakoee, Vladimir Petrovic, Luca Benini:
A multi-banked shared-l1 cache architecture for tightly coupled processor clusters. 1-5 - Davide Zoni, Simone Corbetta, William Fornaciari:
Thermal/performance trade-off in network-on-chip architectures. 1-8 - Christoph Roth, Simon Reder, Gokhan Erdogan, Oliver Sander, Gabriel Marchesan Almeida, Harald Bucher, Jürgen Becker:
Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer. 1-8 - Anja Niedermeier, Jan Kuper, Gerard J. M. Smit:
Dataflow-based reconfigurable architecture for streaming applications. 1-4 - Kun Lu, Daniel Müller-Gritschneder, Ulf Schlichtmann:
Hierarchical control flow matching for source-level simulation of embedded software. 1-5 - Shiao-Li Tsao, Chih-Chen Kao, Ilter Suat, Yuchen Kuo, Yi-Hsin Chang, Cheng-Kun Yu:
PowerMemo: A power profiling tool for mobile devices in an emulated wireless environment. 1-5 - Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel:
Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm2 multi-standard turbo decoder. 1-7 - Jussara Marandola, Stéphane Louise, Loïc Cudennec, Jean-Thomas Acquaviva, David A. Bader:
Enhancing Cache Coherent Architectures with access patterns for embedded manycore systems. 1-7 - Hervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide Bertozzi:
Ultra-low latency NoC testing via pseudo-random test pattern compaction. 1-6 - Roberto Airoldi, Piia Saastamoinen, Jari Nurmi:
Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression. 1-4 - Waqar Hussain, Tapani Ahonen, Jari Nurmi:
Effects of scaling a coarse-grain reconfigurable array on power and energy consumption. 1-5
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