ITC 2010: Austin, TX, USA

Session 1: Building low cost ate in the GHz era

Session 2: Microprocessor test

Session 3: DFT advances

Session 4: Various ATPG techniques

Session 5: Post-silicon validation

Session 6: 3-D Test

Session 7: Memory online test and fault tolerance

Session 8: RF test techniques

Session 9: Scan compression

Session 10: Detecting and understanding defects

Session 11: I love RF

Session 12: Parallel TG and fault simulation and diagnostic TG

Session 13: DFM and yield-learning via design and data analysis

Session 14: DFT for HF ICS

Session 15: Memory testing

Session 16: Advanced topics in board test

Session 17: Faster to market, faster to test: ATE SW advances

Session 18: Mircoprocessor test - At speed learning

Session 19: New issues and enhancements to IEEE 1149.1

Session 20: Ate for when just 1 and 0 is not enough

Session 21: RTL, high-level test and timing emulation

Session 22: Charaterize! Variability, defects, bio-fluidics

Session 23: New ways to test analog

Session 25: Soft-error tolerance and multicore testing

Panel Discussions

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