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ORCIDLCTES 2009: Dublin, Ireland
- Christoph M. Kirsch, Mahmut T. Kandemir:
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009. ACM 2009, ISBN 978-1-60558-356-3
Scheduling
- Eric Stotzer, Ernst L. Leiss:
Modulo scheduling without overlapped lifetimes. 1-10 - Paul Caspi, Jean-Louis Colaço, Léonard Gérard, Marc Pouzet, Pascal Raymond:
Synchronous objects with scheduling policies: introducing safe shared memory in lustre. 11-20 - Taewook Oh, Bernhard Egger
, Hyunchul Park, Scott A. Mahlke:
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures. 21-30 - Jia Zou, Joshua S. Auerbach, David F. Bacon, Edward A. Lee:
PTIDES on flexible task graph: real-time embedded systembuilding from theory to practice. 31-40
Programming languages and compiler
- Jongeun Lee, Aviral Shrivastava:
A compiler optimization to reduce soft errors in register files. 41-49 - Hugh Leather, Michael F. P. O'Boyle, Bruce Worton:
Raced profiles: efficient selection of competing compiler optimizations. 50-59 - Xuejun Yang, Nathan Cooprider, John Regehr:
Eliminating the call stack to save RAM. 60-69 - Sandrine Blazy, Benoît Robillard:
Live-range unsplitting for faster optimal coalescing. 70-79
Architecture and multicores
- Abhik Sarkar, Frank Mueller, Harini Ramaprasad, Sibin Mohan:
Push-assisted migration of real-time tasks in multi-core processors. 80-89 - Jennifer Mankin, David R. Kaeli, John Ardini:
Software transactional memory for multicore embedded systems. 90-98 - Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil:
Synergistic execution of stream programs on multicores with accelerators. 99-108 - Thomas Heinz, Reinhard Wilhelm:
Towards device emulation code generation. 109-118
Runtime system support
- Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson:
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). 119-128 - Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede:
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring. 129-136 - Giovani Gracioli, Sebastian Fischmeister:
Tracing interrupts in embedded software. 137-146 - Ryan W. Moore, José Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser:
Addressing the challenges of DBT for the ARM architecture. 147-156
Validation and verification
- Colin J. Fidge, Diane Corney:
Integrating hardware and software information flow analyses. 157-166 - Charles André, Frédéric Mallet:
Specification and verification of time requirements with CCSL and Esterel. 167-176
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