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ORCID8th MCSoC 2014: Aizu-Wakamatsu, Japan
- IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014, Aizu-Wakamatsu, Japan, September 23-25, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-4305-0
- Huakang Li, Guozi Sun, Bei Xu, Li Li, Jie Huang, Keita Tanno, Wenxu Wu, Changen Xu:
An Information Classification Approach Based on Knowledge Network. 3-8 - Dingding Li, Yong Tang, Bing Liu, Zhendong Yang, Gansen Zhao, Jianguo Li:
A Network-Friendly Disk I/O Optimization Framework in a Virtualized Cloud System. 9-14 - Bin Cao, Li Qiao, Yun Li:
Stackelberg Game Theoretic Approach for Probabilistic Network Coding in Retransmission Mechanism. 15-20 - Ping Lv, Han Wang, Hui Wang:
Phase Distribution Parameter Prediction Using Logistic Model in the Analysis of Two-Phase Flow. 23-30 - Hui Wang, Ping Lv:
Evaluation of Memory Optimization in a Large-Scale Structural Finite Element Pre-processor. 31-38 - Lie Jin, Hongtao Wang, Haitao Wang
, Xinxin Wu:
Numerical Simulation of 3-D Elastic Moduli with Elliptical Cracks Using FM-DBEM. 39-45 - Keiko Igarashi, Saki Seino, Rentaro Yoshioka:
Symbols and Rules for a Self-Explanatory Machine Model. 49-54 - Paul Neve, Gordon Hunter, David Livingstone:
NoobLab: An E-learning Platform for Teaching Programming. 55-62 - Arreytambe Tabot, Mohamed Hamada:
Mobile Learning with Google App Engine. 63-67 - Mohamed Hamada, Aree Muhammed, Kadir Tufan:
Smart Cloud-based Implementation of a Learning Style Index. 68-74 - Deze Zeng, Chao Teng, Hong Yao, Qingzhong Liang, Chengyu Hu, Xuesong Yan:
Stochastic Analysis of Epidemic Routing Based Anycast in Throwbox-Equipped DTNs. 77-81 - Huan Ke, Song Guo, Toshiaki Miyazaki:
Towards Latency-Aware Data Acquisition in Wireless Sensor Network. 82-87 - Takahiro Katagiri, Satoshi Ohshima, Masaharu Matsumoto:
Auto-tuning of Computation Kernels from an FDM Code with ppOpen-AT. 91-98 - Xiong Xiao, Shoichi Hirasawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
An Approach to Customization of Compiler Directives for Application-Specific Code Transformations. 99-106 - Piyu Lee:
Are Mobile Devices More Useful than Conventional Means as Tools for Learning Vocabulary? 109-115 - Martin Ebner, Christoph Prettenthaler, Mohamed Hamada:
Cloud-Based Service for eBooks Using EPUB under the Aspect of Learning Analytics. 116-122 - Hidehito Sawai, Rentaro Yoshioka:
A Format for Work Specification. 123-127 - Ruth Cortez, Alexander Vazhenin, John Brine:
Automatic Glossing Services for E-learning Cloud Environments. 128-131 - Shota Furuya, Katsuki Yanai, Rentaro Yoshioka:
An Analysis Tool for a Programming Contest for High-School Students. 132-137 - Satoru Miyasono, Yosuke Moriai, Hiroshi Saito:
A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based Network-on-Chip Architecture. 141-148 - Artur Podobas:
Accelerating Parallel Computations with OpenMP-Driven System-on-Chip Generation for FPGAs. 149-156 - Nicolas Hili, Christian Fabre, Ivan Llopard, Sophie Dupuy-Chessa, Dominique Rieu:
Model-Based Platform Composition for Embedded System Design. 157-164 - Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
A Thermal Management System for Building Block Computing Systems. 165-171 - Aleksandar Simevski, Rolf Kraemer, Milos Krstic:
Investigating Core-Level N-Modular Redundancy in Multiprocessors. 175-180 - Weiwei Fu, Mingmin Yuan, Tianzhou Chen, Li Liu, Minghui Wu:
SAMNoC: A Novel Optical Network-on-Chip for Energy-Efficient Memory Access. 181-188 - Junxiu Liu, Jim Harkin, Yuhua Li, Liam P. Maguire, Alejandro Linares-Barranco:
Low Overhead Monitor Mechanism for Fault-Tolerant Analysis of NoC. 189-196 - Akram Ben Ahmed, Michael Conrad Meyer, Yuichi Okuyama, Abderazek Ben Abdallah:
Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems. 197-204 - Haruka Mori, Kenji Kise:
Design and Performance Evaluation of a Manycore Processor for Large FPGA. 207-214 - Thiem Van Chu, Shimpei Sato, Kenji Kise:
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. 215-222 - Juan Pedro Cobos Carrascosa, Beatriz Aparicio del Moral, Jose Luis Ramos Mas, Antonio C. López Jiménez, J. C. del Toro Iniesta:
A Multicore Architecture for High-Performance Scientific Computing Using FPGAs. 223-228 - Ahmed Aldammas, Adel Soudani, Abdullah Al-Dhelaan:
A Buffered Flow Control Scheme with Flit Weight-Based Dropping Mechanism for Efficient Communication in NoC. 229-236 - Yuichi Okuyama, Shigeyuki Takano, Tokimasa Shirai:
Design of a Coarse-Grained Processing Element for Matrix Multiplication on FPGA. 237-241 - Tadayoshi Horita, Itsuo Takanami, Masakazu Akiba, Mina Terauchi, Tsuneo Kanno:
A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings. 245-252 - Satoshi Ohshima, Takahiro Katagiri, Masaharu Matsumoto:
Performance Optimization of SpMV Using CRS Format by Considering OpenMP Scheduling on CPUs and MIC. 253-260 - Qiangqiang Shi, Yiyang Yang, Xiaolin Li:
Application of GPU to Three Computational Models. 261-266 - Ta Kang Yen, Bo Yao Yu, Bo-Cheng Charles Lai:
A Cache Aware Multithreading Decision Scheme on GPGPUs. 267-272 - Hamed Khandan:
Introducing A-Cell for Scalable and Portable SIMD Programming. 275-280 - Takahiro Honda, Yukihide Kohira:
An Acceleration for Any-Angle Routing Using Quasi-Newton Method on GPGPU. 281-288 - Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga:
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications. 289-296 - Ali A. El-Moursy:
Adaptive V-Set Cache for Multi-core Processors. 297-302 - Safae Dahmani, Loïc Cudennec, Stéphane Louise, Guy Gogniat:
Using the Spring Physical Model to Extend a Cooperative Caching Protocol for Many-Core Processors. 303-310 - Amr Saleh Elhelw, Ali El-Moursy, Hossam A. H. Fahmy:
Time-Based Least Memory Intensive Scheduling. 311-318 - Hitoshi Ueno:
A Performance Evaluation of Multi-programming Model on a Multicore System with Virtual Machines. 321-328 - Feiyao Wang, Wenyan Wang:
Performance Validation of the Multicore SoC for Spacecraft Applications. 329-332 - Stéphane Louise, Paul Dubrulle, Thierry Goubier:
A Model of Computation for Real-Time Applications on Embedded Manycores. 333-340 - Sourav Dutta, Sheheeda Manakkadu, Dimitri Kagaris:
Classifying Performance Bottlenecks in Multi-threaded Applications. 341-345
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