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ORCIDNANOARCH 2008: Anaheim, CA, USA
- 2008 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2008, Anaheim, CA, USA, June 12-13, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-2552-5
- Sudeep Pasricha, Fadi J. Kurdahi
, Nikil D. Dutt:
System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors. 1-7 - Saturnino Garcia, Alex Orailoglu:
Online test and fault-tolerance for nanoelectronic programmable logic arrays. 8-15 - Christof Teuscher, Natali Gulbahce, Thimo Rohlf:
Assessing random dynamical network architectures for nanoelectronics. 16-23 - Wenjing Rao, Alex Orailoglu, Keith Marzullo:
Locality aware redundancy allocation in nanoelectronic systems. 24-31 - Weiguo Tang, Lei Wang:
A DSP nanosystem with defect tolerance. 32-37 - Ali Namazi, M. Nourami, M. Saquib:
A voterless strategy for defect-tolerant nano-architectures. 38-45 - Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier:
Defect tolerance in QCA-based PLAs. 46-53 - Basheer A. M. Madappuram, Valeriu Beiu, Peter M. Kelly, Liam McDaid:
On brain-inspired connectivity and hybrid network topologies. 54-61 - Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta:
Reconfigurable BDD based quantum circuits. 61-67 - Saleh Safiruddin, Sorin Dan Cotofana, Ferdinand Peper:
Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits. 69-76 - Prateek Mishra, Anish Muttreja, Niraj K. Jha:
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis. 77-84 - Gregory S. Snider:
Spike-timing-dependent learning in memristive nanodevices. 85-92 - Ming Liu, Wei Wang:
rFGA: CMOS-nano hybrid FPGA using RRAM components. 93-98
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