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ORCID13th ReCoSoC 2018: Lille, France
- Smaïl Niar, Mazen A. R. Saghir:
13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2018, Lille, France, July 9-11, 2018. IEEE 2018, ISBN 978-1-5386-7957-9 - Tripti Jain, Klaus Schneider:
Routing Partial Permutations in Interconnection Networks based on Radix Sorting. 1-10 - Georgios Christodoulis, François Broquedis, Olivier Muller, Manuel Selva, Frederic Desprez:
An FPGA target for the StarPU heterogeneous runtime system. 1-8 - Karl Janson
, Rene Pihlak, Siavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Jaan Raik:
AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links. 1-6 - Daniela Genius, Ludovic Apvrille:
System-Level Design and Virtual Prototyping of a Telecommunication Application on a NUMA Platform. 1-8 - David Novo, Alejandro Nocua, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli:
Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing. 1-8 - Junio Cezar Ribeiro da Silva, Fernando Magno Quintão Pereira, Michael Frank, Abdoulaye Gamatié:
A Compiler-Centric Infra-Structure for Whole-Board Energy Measurement on Heterogeneous Android Systems. 1-8 - Charles Leech, Graeme M. Bragg, Domenico Balsamo, Eduardo Wächter:
Application Control and Monitoring in Heterogeneous Multiprocessor Systems. 1-8 - Javier Hoffmann, Dirk Kuschnerus, Trevor Jones, Michael Hübner:
Towards a Safety and Energy Aware protocol for Wireless Communication. 1-6 - Bruno da Silva, Laurent Segers, Yannick Rasschaert, Quentin Quevy, An Braeken, Abdellah Touhafi:
A Multimode SoC FPGA-Based Acoustic Camera for Wireless Sensor Networks. 1-8 - Mohamad-Al-Fadl Rihani, Mohamad Mroué, Jean-Christophe Prévotet, Fabienne Nouvel, Yasser Mohanna:
A Neural Network Based Handover for Multi-RAT Heterogeneous Networks with Learning Agent. 1-6 - Georgios Bousdras, François Quitin, Dragomir Milojevic:
Template architectures for highly scalable, many-core Heterogeneous SoC: Could-of-Chips. 1-7 - Dennis Leander Wolf, Lukas Johannes Jung, Tajas Ruschke, Changgong Li, Christian Hochberger:
AMIDAR Project: Lessons Learned in 15 Years of Researching Adaptive Processors. 1-8 - Brvan Donvanavard, Amir Mahdi Hosseini Monazzah, Nikil D. Dutt, Tiago Mück:
Exploring Hybrid Memory Caches in Chip Multiprocessors. 1-8 - Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck:
Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. 1-8 - Jean-Christophe Le Lann, Théotime Bollengier, Mohamad Najem, Loïc Lagadec:
An Integrated Toolchain for Overlay-centric System-on-chip. 1-8 - Leonardo Suriano, Daniel Madroñal, Alfonso Rodríguez, Eduardo Juárez, César Sanz, Eduardo de la Torre:
A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI. 1-8 - Ashish Chaudhari, Martin Braun:
A Scalable FPGA Architecture for Flexible, Large-Scale, Real-Time RF Channel Emulation. 1-8 - Oliver Körber, Jörg Keller, Simon Holmbacka:
Energy-efficient Execution of Cryptographic Hash Functions on big.LITTLE Architecture. 1-7
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last updated on 2024-09-29 00:11 CEST by the dblp team
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