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ORCIDIEEE Computer Architecture Letters, Volume 14
Volume 14, Number 1, January - June 2015
- Jianwei Liao, Fengxiang Zhang, Li Li, Guoqiang Xiao:
Adaptive Wear-Leveling in Flash-Based Memory. 1-4 - Jie Chen, Guru Venkataramani:
A Hardware-Software Cooperative Approach for Application Energy Profiling. 5-8 - Dae-Hyun Kim
, Prashant J. Nair, Moinuddin K. Qureshi:
Architectural Support for Mitigating Row Hammering in DRAM Memories. 9-12 - Ralph Nathan, Daniel J. Sorin:
Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores. 13-16 - Seongil O, Sanghyuk Kwon, Young Hoon Son, Yujin Park, Jung Ho Ahn:
CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. 17-20 - Ujjwal Gupta, Ümit Y. Ogras:
Constrained Energy Optimizationin Heterogeneous Platforms UsingGeneralized Scaling Models. 21-25 - Amin Farmahini Farahani, Jung Ho Ahn, Katherine Morrow, Nam Sung Kim:
DRAMA: An Architecture for Accelerated Processing Near Memory. 26-29 - Trevor E. Carlson, Siddharth Nilakantan, Mark Hempstead, Wim Heirman:
Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization. 30-33 - Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill, David A. Wood:
gem5-gpu: A Heterogeneous CPU-GPU Simulator. 34-36 - Dilan Manatunga, Joo Hwan Lee, Hyesoon Kim:
Hardware Support for Safe Execution of Native Client Applications. 37-40 - Longjun Liu, Chao Li, Hongbin Sun, Yang Hu, Jingmin Xin, Nanning Zheng, Tao Li:
Leveraging Heterogeneous Power for Improving Datacenter Efficiency and Resiliency. 41-45 - Rui Wang, Wangyuan Zhang, Tao Li, Depei Qian:
Leveraging Non-Volatile Storage to Achieve Versatile Cache Optimizations. 46-49 - Milad Mohammadi, Song Han, Tor M. Aamodt, William J. Dally:
On-Demand Dynamic Branch Prediction. 50-53 - Leonid Azriel, Avi Mendelson, Uri C. Weiser:
Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck. 54-57 - Zhaoguo Wang, Han Yi, Ran Liu, Mingkai Dong, Haibo Chen:
Persistent Transactional Memory. 58-61 - Enric Gibert, Raúl Martínez, Carlos Madriles, Josep M. Codina:
Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units. 62-65 - Daecheol You, Ki-Seok Chung:
Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Embedded GPUs. 66-69 - Sungjin Lee, Jihong Kim, Arvind:
Refactored Design of I/O Architecture for Flash Storage. 70-74 - Fengkai Yuan, Zhenzhou Ji, Suxia Zhu:
Set-Granular Regional Distributed Cooperative Caching. 75-78 - Junghee Lee, Youngjae Kim, Jongman Kim, Galen M. Shipman:
Synchronous I/O Scheduling of Independent Write Caches for an Array of SSDs. 79-82
Volume 14, Number 2, July - December 2015
- Qingchuan Shi, Henry Hoffmann, Omer Khan:
A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads. 85-89 - Zhong Zheng, Zhiying Wang, Mikko H. Lipasti:
Adaptive Cache and Concurrency Allocation on GPGPUs. 90-93 - Tony Nowatzki, Venkatraman Govindaraju, Karthikeyan Sankaralingam:
A Graph-Based Program Representation for Analyzing Hardware Specialization Approaches. 94-98 - Seung-Hun Kim, Dohoon Kim, Changmin Lee, Won Seob Jeong, Won Woo Ro, Jean-Luc Gaudiot:
A Performance-Energy Model to Evaluate Single Thread Execution Acceleration. 99-102 - William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors. 103-106 - Pavan Poluri, Ahmed Louri:
A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems. 107-110 - Canwen Xiao, Yue Yang, Jianwen Zhu:
A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks. 111-114 - Sparsh Mittal, Jeffrey S. Vetter:
AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches. 115-118 - Rajit Manohar:
Comparing Stochastic and Deterministic Computing. 119-122 - Bon-Keun Seo, Seungryoul Maeng, Joonwon Lee, Euiseong Seo:
DRACO: A Deduplicating FTL for Tangible Extra Capacity. 123-126 - Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry:
Fast Bulk Bitwise AND and OR in DRAM. 127-131 - Muhammad Shoaib Bin Altaf, David A. Wood:
LogCA: A Performance Model for Hardware Accelerators. 132-135 - Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris:
Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures. 136-139 - Matthew Poremba, Tao Zhang, Yuan Xie:
NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems. 140-143 - Hans Vandierendonck, Ahmad Hassan, Dimitrios S. Nikolopoulos:
On the Energy-Efficiency of Byte-Addressable Non-Volatile Memory. 144-147 - Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar:
Resistive Associative Processor. 148-151 - Suk Chan Kang, Chrysostomos Nicopoulos, Ada Gavrilovska, Jongman Kim:
Subtleties of Run-Time VirtualAddress Stacks. 152-155 - Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris:
Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS. 156-159 - Nikola Markovic, Daniel Nemirovsky, Osman S. Ünsal, Mateo Valero, Adrián Cristal:
Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core. 160-163 - Gennady Pekhimenko, Evgeny Bolotin, Mike O'Connor, Onur Mutlu, Todd C. Mowry, Stephen W. Keckler:
Toggle-Aware Compression for GPUs. 164-168
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