Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDesign Automation for Embedded Systems, Volume 7
Volume 7, Numbers 1-2, September 2002
- Petru Eles, Zebo Peng:
Editorial. 5-6 - William Fornaciari
, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems. 7-33 - Tony Givargis, Frank Vahid:
Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms. 35-51 - Paolo Gai, Giuseppe Lipari, Marco Di Natale:
Stack Size Minimization for Embedded Real-Time Systems-on-a-Chip. 53-87 - Hongchao (Stephanie) Liu, Xiaobo Sharon Hu:
Processor Utilization Bounds for Real-Time Systems With Precedence Constraints. 89-113 - Cagdas Akturan, Margarida F. Jacome:
An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors. 115-138 - Bilge Saglam Akgul, Vincent John Mooney III:
The System-on-a-Chip Lock Cache. 139-174
Volume 7, Number 3, October 2002
- Luca Benini, Davide Bruni, Mauro Chinosi, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon:
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems. 183-203 - Pai H. Chou, Jinfeng Liu, Dexin Li, Nader Bagherzadeh:
IMPACCT: Methodology and Tools for Power-Aware Embedded Systems. 205-232 - André Nieuwland, Jeffrey Kang, Om Prakash Gangwal, Ramanathan Sethuraman, Natalino G. Busá, Kees Goossens, Rafael Peset Llopis, Paul E. R. Lippens:
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems. 233-270 - Fabian Wolf, Jan Staschulat, Rolf Ernst:
Hybrid Cache Analysis in Running Time Verification of Embedded Software. 271-295
Volume 7, Number 4, November 2002
- Ed F. Deprettere, Bart Kienhuis, Richard L. Walke:
Preface. 303-305 - Neal K. Bambha, Vida Kianzad, Mukul Khandelia, Shuvra S. Bhattacharyya:
Intermediate Representations for Design Automation of Multiprocessor DSP Systems. 307-323 - Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar:
Improving Software Performance with Configurable Logic. 325-339 - Jozsef Ludvig, James G. McCarthy, Stephen Neuendorffer, Sonia R. Sachs:
Reprogrammable Platforms for High-Speed Data Acquisition. 341-364 - Patrick Schaumont, Ingrid Verbauwhede:
Domain Specific Tools and Methods for Application in Security Processor Design. 365-383 - Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere:
Compilation From Matlab to Process Networks Realized in FPGA. 385-403
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-18 20:20 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
