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ORCIDJournal of Electronic Testing, Volume 5
Volume 5, Number 1, February 1994
- Vishwani D. Agrawal:
Editorial. 5 - Angus Wu
, Jack L. Meador:
Measurement selection for parametric IC fault diagnosis. 9-18 - Fadi Y. Busaba, Parag K. Lala:
Self-checking combinational circuit design for single and unidirectional multibit error. 19-28 - Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man:
Design of a C-testable booth multiplier using a realistic fault model. 29-41 - Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja:
Incorporating testability considerations in high-level synthesis. 43-55 - Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell:
Energy minimization and design for testability. 57-66 - Dipanwita Roy Chowdhury, Indranil Sengupta, Parimal Pal Chaudhuri:
A class of two-dimensional cellular automata and their applications in random pattern testing. 67-82 - Slawomir Pilarski, André Ivanov, Tiko Kameda:
On minimizing aliasing in scan-based compaction. 83-90 - Bruce F. Cockburn:
Deterministic tests for detecting singleV-coupling faults in RAMs. 91-113 - Enrico Macii, Angelo Raffaele Meo:
A test generation program for sequential circuits. 115-119
Volume 5, Numbers 2-3, May 1994
- Vishwani D. Agrawal:
Editorial. 127 - Magdy S. Abadir, Tony Ambler:
Introduction. 129-130 - Vishwani D. Agrawal:
A tale of two designs: the cheapest and the most economic. 131-135 - I. D. Dear, Chryssa Dislis, Anthony P. Ambler, J. H. Dick:
Test strategy planning using economic analysis. 137-155 - Brendan Davis:
Economic modeling of board test strategies. 157-169 - Farzad Zarrinfar:
Economics of "design for test" to remain competitive in the 90s. 171-177 - Prab Varma, Tushar Gheewala:
The economics of scan-path design for testability. 179-193 - Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy:
High Level Test Economics Advisor (Hi-TEA). 195-206 - Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh:
Multichip systems trade-off analysis tool. 207-218 - Shekar Rao, Bert Haskell, Ian Yee:
Trade-off analysis on cost and manufacturing technology of an electronic product: Case study. 219-228 - Mathew Alexander, K. Sríhari, C. Robert Emerson:
Cost based surface mount PCB design evaluation. 229-238 - J. H. Dick, Erwin Trischler, Chryssa Dislis, Anthony P. Ambler:
Sensitivity analysis in economics based test strategy planning. 239-251 - Steven D. Millman:
Improving quality: Yield versus test coverage. 253-261 - Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Boundary scan in board manufacturing. 263-268 - Christian von Reventlow:
Comparing quality assurance methods and the resulting design strategies: Experiences from complex designs. 269-272 - Michael Nicolaidis, O. Kebichi, Vladimir Castro Alves:
Trade-offs in scan path and BIST implementations for RAMs. 273-283 - Amitava Majumdar, Sarma B. K. Vrudhula:
Techniques for estimating test length under random test. 285-297 - Mounir Fares, Bozena Kaminska:
Fuzzy optimization models for analog test decisions. 299-305 - Arno Kunzmann, Frank Böhland:
Self-test of sequential circuits with deterministic test pattern sequences. 307-312
Volume 5, Number 4, November 1994
- Vishwani D. Agrawal:
Editorial. 317 - Pinaki Mazumder:
Guest editor's introduction. 319-320 - Bruce F. Cockburn:
Tutorial on semiconductor memory testing. 321-336 - Ad J. van de Goor, Yervant Zorian:
Effective march algorithms for testing single-order addressed memories. 337-345 - Kanad Chakraborty, Pinaki Mazumder:
Technology and layout-related testing of static random-access memories. 347-365 - Kewal K. Saluja:
On-chip testing of random access memories. 367-376 - O. Kebichi, Vyacheslav N. Yarmolik, Michael Nicolaidis:
Zero aliasing ROM BIST. 377-388
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