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Integration, Volume 11
Volume 11, Number 1, March 1991
- Lambert Spaanenburg:

Editorial. 1 - Paola Favati

, Grazia Lotti, Francesco Romani
:
VLSI implementation of the capacitance matrix method. 3-9 - Yeu-Shen Jehng, Liang-Gee Chen

, Tai-Ming Parng:
ASG: Automatic schematic generator. 11-27 - G. A. Chukwudebe, Raouf N. Gorgui-Naguib

, Satnam Singh Dlay:
Sparse matrix superchip: A reconfigurable architecture for VLSI processing arrays. 29-42 - Ta-Yung Liu, Youn-Long Lin:

FLORA: A data path allocator based on branch-and-bound search. 43-66 - Ferruccio Barsi, Enrico Martinelli:

A VLSI architecture for RNS with MI adders. 67-83 - Dirk Timmermann

, Helmut Hahn, Bedrich J. Hosticka, Bernold Rix:
A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms. 85-100
Volume 11, Number 2, April 1991
- Lambert Spaanenburg:

Editorial. 109 - Elena Lodi, Fabrizio Luccio, Xiaoyu Song:

A 2d channel router for the diagonal model. 111-125 - Majid Sarrafzadeh:

Tree placement in Cascode-Switch macros. 127-139 - C. P. Ravikumar, Sarma Sastry:

VYUHA: A detailed router for multiple routing models. 141-157 - Kamal Chaudhary, Peter Robinson:

Routing in and around a rectangle using the overlap model. 159-167 - Khaled M. Elleithy

, Magdy A. Bayoumi, Lois M. L. Delcambre:
VLSI implementation of a systolic database machine for relational algebra and hashing. 169-190 - Chong-Min Kyung, Peter V. Kraus, Dieter A. Mlynski:

An analytic algorithm for global circuit placement. 191-204
Volume 11, Number 3, June 1991
- Lambert Spaanenburg:

Editorial. 213 - Nany Hasan, C. L. Liu:

Minimum fault covering in reconfigurable arrays. 215-234 - David A. Basin, Geoffrey M. Brown, Miriam Leeser

:
Formally verified synthesis of combinational CMOS circuits. 235-250 - Donatella Sciuto

:
Testability conditions for two-dimensional bilateral arrays. 251-278 - Wei-Kang Huang, Fabrizio Lombardi:

Minimizing the cost of repairing WSI memories. 279-293 - Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong:

Planar topological routing of pad nets. 295-316 - N. Q. Thang:

A logic minimization algorithm of functions with large DC-set. 317-327

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