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ORCIDIntegration, Volume 71
Volume 71, March 2020
- Ziran Zhu, Zhipeng Huang, Peng Yang, Wenxing Zhu, Jianli Chen, Hanbin Zhou, Senhua Dong:
Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect. 1-10
- Bernhard Lippmann, Niklas Unverricht, Aayush Singla, Matthias Ludwig
, Michael Werner, Peter Egger, Anja Dübotzky, Helmut Gräb, Horst A. Gieser, Martin Rasche, Oliver Kellermann:
Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies. 11-29
- Shang Ma, Wei Cao, Shengqiang Jiang, Jianhao Hu, Xin Lei, Xiongzhong Xiong:
Design and implementation of SVM OTPC searching based on Shared Dot Product Matrix. 30-37
- Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes:
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. 38-48
- Jiankai Tu, Qinming Zhang, Chenyang Zhang, Chengwei Zhou:
A Noise-Aware Real-Time Processing Approach for Electroencephalogram Signal Classification. 49-55
- Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza:
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. 56-69
- Jijun Ren:
Digital predistorter with improving index accuracy of lookup table based on FPGA. 70-75 - Jongsung Kang, Taewhan Kim:
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks. 76-85 - Mostafa Jafari-Nodoushan, Alireza Ejlali:
An optimal analytical solution for maximizing expected battery lifetime using the calculus of variations. 86-94 - Fadi Riad Shahroury:
Design of a low-power CMOS transceiver for semi-passive wireless sensor network application. 95-104 - Hongmei Chen, Yongsheng Yin, Tao Liu, Linhao Gan, Rui Xiao, Hui Yan, Honghui Deng:
A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC. 105-114 - Pratosh Kumar Pal, Rajendra Kumar Nagaria:
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load. 115-124 - Phrangboklang Lyngton Thangkhiew, Alwin Zulehner, Robert Wille, Kamalika Datta, Indranil Sengupta:
An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD). 125-133 - K. Sravani, Rathnamala Rao:
A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding. 134-143 - Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike:
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. 144-153 - Mohammad Eslami, Behnam Ghavami, Mohsen Raji, Ali Mahani:
A survey on fault injection methods of digital integrated circuits. 154-163 - Fotios Ntouskas, Constantinos Efstathiou, Kiamal Z. Pekmestzi:
Efficient design of magnitude and 2's complement comparators. 164-169 - Pallab Kumar Nath, Swapna Banerjee:
A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process. 170-182
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