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IEEE Journal of Solid-State Circuits, Volume 24
Volume 24, Number 1, February 1989
- Robert G. Meyer, William D. Mack:
A wide-band class AB monolithic power amplifier. 7-12 - Toshihiko Shimizu, Masao Hotta, Kenji Maio, Seiichi Ueda:
A 10-bit 20-MHz two-step parallel A/D converter with internal S/H. 13-20 - Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara:
Twisted bit-line architectures for multi-megabit DRAMs. 21-27 - Lawrence T. Clark, Robert O. Grondin:
A pipelined associated memory implemented in VLSI. 28-34 - Yasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara:
Analysis of coupling noise between adjacent bit lines in megabit DRAMs. 35-42 - Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima:
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. 43-49 - Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko:
A built-in Hamming code ECC circuit for DRAMs. 50-56 - Alex Yuen, Peter Tsao, Patrick Yin, Albert T. Yuen:
A 32 K ASIC synchronous RAM using a two-transistor basic cell. 57-61 - Jiren Yuan, Christer Svensson:
High-speed CMOS circuit technique. 62-70 - Sterling R. Whitaker, Gary K. Maki:
Pass-transistor asynchronous sequential circuits. 71-78 - Paul Layman, Savvas G. Chamberlain:
A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits. 79-89 - Geert P. Rosseel, Robert W. Dutton:
Influence of device parameters on the switching speed of BiCMOS buffers. 90-99 - Erik Bruun:
Reverse-voltage protection methods for CMOS circuits. 100-103 - Tho T. Vu, James M. Hattis:
A GaAs phase digitizing and summing system for microwave signal storage. 104-117 - Charles G. Sodini, S. Simon Wong, Ping Keung Ko:
A framework to evaluate technology and device design enhancements for MOS integrated circuits. 118-127 - James W. Roberts, Savvas G. Chamberlain:
A CMOS model for computer-aided circuit analysis and design. 128-138 - Shreepad Karmalkar
, Kartik N. Bhat:
A process-parameter-based circuit simulation model for ion-implanted MOSFETs and MESFETs. 139-145 - Jens U. Horstmann, Hans W. Eichel, Robert L. Coates:
Metastability behavior of CMOS ASIC flip-flops in theory and test. 146-157 - M. Jamal Deen
:
Digital characteristics of CMOS devices at cryogenic temperatures. 158-164 - David D. Slater, John J. Paulos:
Low-voltage coefficient capacitors for VLSI processes. 165-173 - Sui-Ping Shieh, Chorng-Kuang Wang, Rinaldo Castello
, Paul R. Gray:
A scalable switched-capacitor filter implemented in 1.25- mu m technology. 174-177 - Chung-Yu Wu, Tsai-Chung Yu, Shin-Shi Chang:
New monolithic switched-capacitor differentiators with good noise rejection. 177-180 - Krishnaswamy Nagaraj:
Large-swing CMOS buffer amplifier. 181-183 - Jeff Fried, Elizabeth Daly, Ted Lyszczarz, Michael Copperman:
A memory-controlled crosspoint switch using E-beam restructuring. 183-187 - Xiaonan N. Zhang:
Calculation of critical charge of bipolar memory circuits. 187-189 - Denis J. F. Doyle, William A. Lane:
Circuit modeling of bipolar transistors for BiCMOS. 189-193 - Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana:
CMOS stuck-open fault testability. 193-194 - Charles Longway, Raymond Siferd:
A doughnut layout style for improved switching speed with CMOS VLSI gates. 194-198
Volume 24, Number 2, April 1989
- Valdis E. Garuts, Yeou-Chong Simon Yu, Einar O. Traa, Tadanori Yamaguchi:
A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter using a 70-ps silicon bipolar technology with borosenic-poly process and coupling-base implant. 216-222 - Francois Thomas, Francis Debrie, Maurice Gloanec, Michele Le Paih, Philippe Martin, Thao Nguyen, Stephanie Ruggeri, Jean-Marie Uro:
1-GHz GaAs ADC building blocks. 223-228 - Oscar E. Agazzi, Alberto A. Adan:
An analog front end for full-duplex digital transceivers working on twisted pairs. 229-240 - Joey Doernberg, Paul R. Gray, David A. Hodges:
A 10-bit 5-Msample/s CMOS two-step flash ADC. 241-249 - Donald A. Kerth, Navdeep S. Sooch, Eric J. Swanson:
A 12-bit, 1-MHz, two-step flash ADC. 250-255 - Steven R. Norsworthy, Irving G. Post, H. Scott Fetterman:
A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation. 256-266 - L. Richard Carley:
A noise-shaping coder topology for 15+ bit converters. 267-273 - Vladimir Friedman, Douglas M. Brinthaupt, De-Ping Chen, Timothy W. Deppa, John P. Elward Jr., Evelyn M. Fields, Jeffrey W. Scott, T. R. Viswanathan:
A dual-channel voice-band PCM codec using Sigma Delta modulation technique. 274-280 - Steven J. Daubert, David W. Green, John Khoury, James M. Trosino, Ed Zimany, Jeffrey R. Barner, Joseph Plany, Michael F. Tompsett:
A CMOS modem analog processor for V.22 bis modems. 281-291 - Larry J. Stotts, K. Ross Infinger, Janet Babka, David Genzer:
An 8-bit microcomputer with analog subsystems for implantable biomedical application. 292-300 - Francois Callias, Francois H. Salchli, Dominique Girard:
A set of four ICs in CMOS technology for a programmable hearing aid. 301-312 - Daniel B. Schwartz, Richard E. Howard, Wayne E. Hubbard:
A programmable analog neural network chip. 313-319 - Bang-Sup Song:
A 10.7-MHz switched-capacitor bandpass filter. 320-324 - Sam Yinshang Sun:
An analog PLL-based clock and data recovery circuit with high input jitter tolerance. 325-330 - James A. Gasbarro, Mark A. Horowitz:
Integrated pin electronics for VLSI functional testers. 331-337 - Peter A. Ruetz:
The architectures and design of a 20-MHz real-time DSP chip set. 338-348 - Georges Quénot, Jean-Luc Gauvain, Jean-Jacques Gangolf, Joseph-Jean Mariani:
A dynamic programming processor for speech recognition. 349-357 - Inseok Hwang, Aaron L. Fisher:
Ultrafast compact 32-bit CMOS adders in multiple-output domino logic. 358-369 - Larry D. Smith, Henry R. Farmer, Marie Kunesh, Michael A. Massetti, Dennis R. Willmott, Robert Hedman, Ray Richetta, Timothy J. Schmerbeck:
A CMOS-based analog standard cell product family. 370-379 - Fu-Tai Liou, Yu-Pin Han, Frank R. Bryant, Mehdi Zamanian:
A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array. 380-387 - Tohru Furuyama, Takashi Ohsawa
, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori:
An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. 388-393 - Abbas El Gamal, Jonathan W. Greene, Justin Reyneri, Eric Rogoyski, Khaled A. El-Ayat, Amr Mohsen:
An architecture for electrically configurable gate arrays. 394-398 - Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
:
Boolean decomposition in multilevel logic optimization. 399-408 - Catherine H. Gebotys, Mohamed I. Elmasry:
Integration of algorithmic VLSI synthesis with testability incorporation. 409-417 - Jeff Rijmenants, James B. Litsios, Thomas R. Schwarz, Marc G. R. Degrauwe:
ILAC: an automated layout tool for analog CMOS circuits. 417-425 - Baher Haroun, Mohamed I. Elmasry:
SPAID: an architectural synthesis tool for DSP custom applications. 426-435 - Ronald S. Gyurcsik, Jzan-Ching Jeen:
A generalized approach to routing mixing analog and digital signal nets in a channel. 436-442 - Kenneth S. Kundert, Jacob White, Alberto L. Sangiovanni-Vincentelli
:
A mixed frequency-time approach for distortion analysis of switching filter circuits. 443-451 - Theologos M. Kelessoglou, Donald O. Pederson:
NECTAR: a knowledge-based environment to enhance SPICE. 452-457 - David F. Frost, Kelvin Fang:
RELIANT: a reliability analysis tool for VLSI interconnect. 458-462 - Bruce Cheney, Pat Hamilton, George LaRue:
Design and test of a 2-Gbit/s GaAs 16/8-bit MUX/DEMUX pair. 463-466 - Wayne P. Burleson, Louis L. Scharf, Arthur R. Gabriel, Neil H. Endsley:
A systolic VSLI chip for implementing orthogonal transforms. 466-469 - James McDonald, Rajnish Maini, Lee Spangler, Harrison Weed:
Response surface methodology: a modeling tool for integrated circuit designers. 469-473 - Bing J. Sheu, Wen-Jay Hsu, Bang W. Lee:
An integrated-circuit reliability simulator-RELY. 473-477 - Hyun J. Shin, David A. Hodges:
A 250-Mbit/s CMOS crosspoint switch. 478-486 - Mark R. Santoro, Mark A. Horowitz:
SPIM: a pipelined 64*64-bit iterative multiplier. 487-493 - Magdy A. Bayoumi, Nam Ling:
Testing of a NORA CMOS serial-parallel multiplier. 494-503 - Bor-Yuan Hwang, Thomas P. Bushey, James A. Kirchgessner, Samuel A. Foertsch, James J. Stipanuk, Larry Marshbanks, Juan A. Hernandez, Eric R. Herald:
A bipolar ECL static RAM using polysilicon-diode loaded memory cell. 504-511 - Peter Ashburn, Ali A. Rezazadeh, Eng-Fong Chor, Arthur Brunnschweiler:
Comparison of silicon bipolar and GaAlAs/GaAs heterojunction bipolar technologies using a propagation delay expression. 512-519 - Antonio M. Martinez:
Quick estimation of transient currents in CMOS integrated circuits. 520-531 - Norman Scheinberg, Robert Bayruns, Phililip W. Wallace, Ravender Goyal:
An accurate MESFET model for linear and microwave circuit design. 532-539 - Peter M. Van Peteghem, J. Francisco Duque-Carrillo
:
Compact high-frequency output buffer for testing of analog CMOS VLSI circuits. 540-542 - Theodore L. Tewksbury, Hae-Seung Lee, Gerald A. Miller:
The effects of oxide traps on the large-signal transient response of analog MOS circuits. 542-544
Volume 24, Number 3, June 1989
- Maurice P. Depey, Francis Dell'ova, Jean-Marc Chateau, Catherine Mallardeau, Albert J. Fryers, Klaus Woerner:
A 10 K-gate 950 MHz CML demonstrator circuit made with a 1- mu m trench-isolated bipolar silicon technology. 552-557 - Albrecht Rothermel, Bedrich J. Hosticka, Gerhard Tröster, Juergen Arndt:
Realization of transmission-gate conditional-sum (TGCS) adders with low latency time. 558-561 - Michel Verleysen, Bruno Sirletti, Andre M. Vandemeulebroecke, Paul G. A. Jespers:
Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm. 562-569 - Jürgen Kernhof, Michiel A. Beunder, Bernd Hoefflinger, Werner Haas:
High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment. 570-575 - Philippe Duchene, Michel J. Declercq:
A highly flexible sea-of-gates structure for digital and analog applications. 576-584 - Philip J. Smith, P. Birdsall, Colin T. Mallett:
Gallium-arsenide buffer store components for Gbit/s optical-fiber transmission systems. 585-591 - A. Kemal Goksel, Robert H. Krambeck, Philipp P. Thomas, Mean-Sea Tsay, Cheng Yueh Chen, Donald G. Clemons, Frank D. LaRocca, Liang-Peng Mai:
A content addressable memory management unit with on-chip data cache. 592-596 - Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara
, Tetsuro Matsumoto, Yutaka Kobayashi:
A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. 597-602 - Yiannos Manoli:
A self-calibration method for fast high-resolution A/D and D/A converters. 603-608 - Andrew K. Joy, Anthony J. Holden, Thomas C. Leslie, Peter H. Saul:
A comparison of GaAs HJBT and silicon bipolar technologies for high-speed analog-to-digital converters. 609-616 - Bertram Rodgers, Charles R. Thurber:
A monolithic +or-5 1/2-digit BiMOS A/D converter. 617-626 - Sietse E. Wouters, Weijian Lian:
A flip-flop sensor array with on-spot A/D conversion. 627-634 - Alessandro Cremonesi, Franco Maloberti, Gino Polito:
A 100-MHz CMOS DAC for video-graphic systems. 635-639 - Burkhard Giebel, Jürgen Lutz, Paul O'Leary:
Digitally controlled oscillator. 640-645 - Paul T. M. van Zeijl:
A new high-dynamic range dual-loop power-to-current amplifier. 646-650 - Remco J. Wiegerink
, Evert Seevinck, Wim De Jager:
Offset cancelling circuit. 651-658 - Marc G. R. Degrauwe, Bernard L. A. G. Goffart, Christian Meixenberger, Michel L. A. Pierre, James B. Litsios, Jef Rijmenants, Olivier J. A. P. Nys, Evert Dijkstra, Bernie Joss, Myriam K. C. M. Meyvaert, Thomas R. Schwarz, Matthijs D. Pardoen:
Towards an analog system design environment. 659-671 - Hans Wallinga, Klaas Bult:
Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model. 672-680 - Elve D. J. Moons, Eddie Willocx, Dirk Rabaey:
Fully integrated analog telephone. 681-685 - Peter J. Topham, Adrian P. Long, Peter H. Saul, J. Greg Parton, Brian A. Hollis, Nicholas A. Hiams, Robert C. Goodfellow:
A broad-band amplifier using GaAs/GaAlAs heterojunction bipolar transistors. 686-689 - Marco Ferro, Franco Salerno, Rinaldo Castello
:
A floating CMOS bandgap voltage reference for differential applications. 690-697 - David J. Pedder:
Interconnection and packaging of solid-state circuits. 698-703 - John V. Hatfield, Trevor A. York, John Comer, Peter J. Hicks:
Development of a new type of self-scanned electron image sensing integrated circuit. 704-710 - Eiji Oda, Kenji Nagano, Takanori Tanaka, Nobuhiko Mutoh, Kozo Orihara:
A 1920(H)*1035(V) pixel high-definition CCD image sensor. 711-717 - Uwe Schoeneberg, Bedrich J. Hosticka, Jürgen Fent, Horst Oberlack, Günter Zimmer:
CMOS readout electronics for operation at cryogenic temperatures. 718-722 - Mario Sartori, Michelangelo Mazzucco, Roberto Gaidano:
ALBA: a bipolar technology structured array for the design of high-order continuous-time filters. 723-731 - Colin L. Perry:
An integrated continuous-time bipolar transconductor-capacitor filter. 732-735 - Andreas Kaiser
:
A micropower CMOS continuous-time low-pass filter. 736-743 - R. Klinke, Bedrich J. Hosticka, Hans-Jörg Pfleiderer:
A very-high-slew-rate CMOS operational amplifier. 744-746 - William J. McFarland, Kent H. Springer, Chu-Sun Yen:
1-Gword/s pseudorandom word generator. 747-751 - Khaled A. El-Ayat, Abbas El Gamal, Richard Guo, John Chang, Ricky K. H. Mak, Frederick Chiu, Esmatz Z. Hamdy, John McCollum, Amr Mohsen:
A CMOS electrically configurable gate array. 752-762 - Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka:
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. 763-770 - Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara
, Tetsuro Matsumoto:
Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. 771-778 - Jinn-Shyan Wang, Chung-Yu Wu, Ming-Kai Tsai:
CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications. 779-786 - Mehmet Soyuer, Robert G. Meyer:
High-frequency phase-locked loops in monolithic bipolar technology. 787-795 - Robert J. Widlar, Mineo Yamatake:
A fast-settling op amp with low supply current. 796-802 - Germano Nicollini, Francesco Moretti, Mauro Conti:
High-frequency fully differential filter using operational amplifiers without common-mode feedback. 803-813 - Robert Bayruns, Elizabeth A. Hofstatter, Harry T. Weston:
A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set. 814-821 - Kyo Y. Chung, Gerold W. Neudeck:
Transient analysis of the CMOS-like a-Si:H TFT inverter circuit. 822-829 - Masahiko Sumi, Shigeru Tanaka, Naoyuki Kai, Yuichi Miyazawa, Masato Nagamatsu, Tsutomu Minagawa, Ichiro Nagashima, Tsuneo Hamai, Junji Mori, Tatsuo Noguchi:
A 40-Mpixel/s bit block transfer graphics processor. 830-835 - A. J. M. Montagne, M. Kleefstra:
A straightforward parallel-in, serial-out filter with a junction charge-coupled device and an integrated clock driver. 835-838 - Yosi Shacham-Diamand, Alex Sinar, Eric Sirkin, Ilan Blech, Levy Gerzberg:
A bridge circuit for the characterization of electrically programmable elements. 839-841 - Jeffrey A. Dykstra, Richard B. Brown:
A comparison of gold and superconductors used as air-bridge and microstrip interconnects for high-speed VLSI. 842-844 - Ghassan Y. Yacoub, Walter H. Ku:
An enhanced technique for simulating short-circuit power dissipation. 844-847
Volume 24, Number 4, August 1989
- Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle:
A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces. 859-868 - Shuji Murakami, Katsuki Ichinose, Kenji Anami, Shimpei Kayano:
Improvement of soft-error rate in MOS SRAMs. 869-873 - Peter H. Voss, Leo C. M. G. Pfennings, Cathal G. Phelan, Cormac M. O'Connell, Thomas J. Davies, Hans Ontrop, Simon A. Bell, Roelof H. W. Salters:
A 14 ns 256 K*1 CMOS SRAM with multiple test modes. 874-880 - Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato:
A 32 kbyte integrated cache memory. 881-888 - Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh:
New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. 889-894 - Rainer Kraus, Kurt Hoffmann:
Optimized sensing scheme of DRAMs. 895-899 - Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi:
New nibbled-page architecture for high-density DRAMs. 900-904 - Yohji Watanabe, Takashi Ohsawa
, Kiyofumi Sakurai, Tohru Furuyama:
A new CR-delay circuit technology for high-density and high-speed DRAMs. 905-910 - Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara:
A 5 V only one-transistor 256 K EEPROM with page-mode erase. 911-915 - Takahiro Hanyu, Tatsuo Higuchi:
High-density quaternary logic array chip for knowledge information processing systems. 916-921 - Ramautar Sharma, Alexander D. Lopez, John A. Michejda, Steven J. Hillenius, John M. Andrews, Arnold J. Studwell:
A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology. 922-927