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ORCIDIEEE Journal of Solid-State Circuits, Volume 25
Volume 25, Number 1, February 1990
- Mikio Asakura, Yoshio Matsuda, Hidaka Hidaka, Yoshinori Tanaka, Kazuyasu Fujishima:
An experimental 1-Mbit cache DRAM with ECC. 5-10 - Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima:
A speed-enhanced DRAM array architecture with embedded ECC. 11-17 - Jun-ichi Okamura, Yoshio Okada, Masaru Koyanagi, Yoshiaki Takeuchi, Masahiro Yamada, Kiyofumi Sakurai, Sadao Imada, Suzuo Saito:
Decoded-source sense amplifier for high-density DRAMs. 18-23 - Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka:
The stabilized reference-line (SRL) technique for scaled DRAMs. 24-29 - Hisakazu Kotani, Hironori Akamatsu, Junko Matsushima, Shozo Okada, Tsuyoshi Shiragasawa, Takayoshi Yamada, Michihiro Inoue:
A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier. 30-35 - Hiroyuki Yamauchi, Toshiki Yabu, Takayoshi Yamada, Michihiro Inoue:
A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers. 36-41 - Tohru Furuyama, Hidemi Ishiuchi, Hiroyasu Tanaka, Yoshihisa Watanabe, Yusuke Kohyama, Tohru Kimura, Kazuyoshi Muraoka, Souichi Sugiura, Kenji Natori:
A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs. 42-47 - Wolfgang Heimsch, Roland Krebs, Bruno Pfaffel, Klaus Ziemann:
A 3.8-ns 16 K BiCMOS SRAM. 48-54 - Koichiro Ishibashi, Toshiaki Yamanaka, Katsuhiro Shimohigashi:
An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell. 55-60 - Clinton Kuo, Thomas Toms, Bruce T. Neel, Joe Jelemensky, Ernest A. Carter, Philip Smith:
Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM. 61-67 - Fumio Miyaji, Takashi Emori, Yasushi Matsuyama, Yoshikazu Kanaishi, Katsunori Seno, Yoshiaki Hagiwara:
A multibit test trigger circuit for megabit SRAMs. 68-71 - Kenichi Imamiya, Jun-ichi Miyamoto, Shigeru Atsumi, Nobuaki Ohtsuka, Yukinori Muroya, Toshiyuki Sako, Masao Higashino, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Hitoshi Araki, Yukio Kaneko, Kazuhito Narita, Norihisa Arai, Kuniyoshi Yoshikawa, Shinichi Tanaka:
A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. 72-78 - Kiyoteru Kobayashi, Tatsuo Nakayama, Yoshikazu Miyawaki, Masanori Hayashikoshi, Yasushi Terada, Tsutomu Yoshihara:
A high-speed parallel sensing architecture for multi-megabit flash E/sup 2/PROMs. 79-83 - Gregory A. Uvieghara, Yoshinobu Nakagome, Deog-Kyoon Jeong, David A. Hodges:
An on-chip smart memory for a data-flow CPU. 84-94 - Hidehiro Takata, Shinji Komori, Toshiyuki Tamura, Fumiyasu Asai, Hisakazu Sato, Takio Ohno, Takeshi Tokuda, Hiroki Nishikawa, Hirofumi Terada:
A 100-mega-access per second matching memory for a data-driven microprocessor. 95-99 - Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka:
A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. 100-108 - Mitsumasa Koyanagi, Hidehiro Takata, Hiroki Mori, Junichiro Iba:
Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system. 109-116 - Seigo Kotani, Takahiro Imamura, Shinya Hasuo:
A subnanosecond clock Josephson 4-bit processor. 117-124 - Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi:
Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems. 125-131 - Akira Kanuma, Toshiyuki Yaguchi, Koichi Tanaka, Eiichi Katsumata, Katsuhito Fujimoto, Yuuichi Miyazawa, Shinichi Iida, Takeshi Yamamoto:
A CMOS 510 K-transistor single-chip token-ring LAN controller (TRC) compatible with IEEE802.5 MAC protocol. 132-141 - James D. Gallia, Ah-Lyan Yee, Kwok Kit Chau, I-Fay Wang, Harvey Davis, Shobana Swamy, Van M. Nguyen, Kamalesh Natvarlal Ruparel, Kermit Moore, Brian Chae, Carl E. Lemonds, Pat Eyres, Toshiaki Yoshino, Ashwin Shah:
High-performance BiCMOS 100 K-gate array. 142-149 - Hans-Jürgen Schumacher, Jan Dikken, Evert Seevinck:
CMOS subnanosecond true-ECL output buffer. 150-154 - Masao Suzaki, Naoki Yamanaka, Michihiro Hirata, Shiro Kikuchi:
A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs. 155-159 - Anthony Jayakumar, Kenneth C. Young Jr.:
A 70-Mbit/s (RZ) 16*16 crosspoint switch for ternary-encoded signals. 160-166 - Shiro Hosotani, Takahiro Miki, A. Maeda, N. Yazawa:
An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption. 167-172 - Richard K. Hester, Khen-Sang Tan, Michiel de Wit, John W. Fattaruso, Sami Kiriaki, James R. Hellums:
Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation. 173-183 - Christopher Wood Mangelsdorf:
A 400-MHz input flash converter with error correction. 184-191 - Peter J. Lim, Bruce A. Wooley:
An 8-bit 200-MHz BiCMOS comparator. 192-199 - Tsutomu Wakimoto, Yukio Akazawa:
A low-power wide-band amplifier using a new parasitic capacitance compensation technique. 200-206 - Francis J. Kub, Keith K. Moon, Ingham A. Mack, Francis M. Long:
Programmable analog vector-matrix multipliers. 207-214 - Peter H. Saul, David G. Taylor:
A high-speed direct frequency synthesizer. 215-219 - Mitsuru Shinagawa, Yukio Akazawa, Tsutomu Wakimoto:
Jitter analysis of high-speed sampling systems. 220-224 - Morteza Afghahi, Christer Svensson:
A unified single-phase clocking scheme for VLSI systems. 225-233 - Kobchai Dejhan, Nicolas Demassieux, Oswald Colavin, Arnaud Galisson, Alain Artieri, Francis Jutand:
Design of a low-power 32 K CMOS programmable delay-line memory. 234-238 - Hausila P. Singh, Robert A. Sadler, William J. Tanis, Alan N. Schenberg:
GaAs prescalers and counters for fast-settling frequency synthesizers. 239-245 - Niraj K. Jha:
Testing of differential cascode voltage switch one-count generators. 246-253 - Leonardo M. Reyneri, Dante Del Corso, Bruno Sacco:
Oscillatory metastability in homogeneous and inhomogeneous flip-flops. 254-264 - Frank N. L. Op't Eynde, Patrick F. M. Ampe, Lode Verdeyen, Willy M. C. Sansen:
A CMOS large-swing low-distortion three-stage class AB power amplifier. 265-273 - Richard R. Spencer, James B. Angell:
A voltage-controlled duty-cycle oscillator. 274-281 - William Redman-White, Roy Dunn, Rex Lucas, Peter Smithers:
A radiation-hard AGC stabilized SOS crystal oscillator. 282-288 - Eduard Sackinger, Walter Guggenbuhl:
A high-swing, high-impedance MOS cascode circuit. 289-298 - Philip C. Canfield, Steven C. F. Lam, David J. Allstot:
Modeling of frequency and temperature effects in GaAs MESFETs. 299-306 - A. A. Sharratt, S. Ward:
Comparison of current-switched logic gates for high-speed communications applications. 307-309 - Ted E. Williams, Mark Horowitz:
Bipolar circuit elements providing self-completion-indication. 309-312 - S. Khursheed Enam, Asad A. Abidi:
A 300-MHz CMOS voltage-controlled ring oscillator. 312-315 - Zhenhua Wang, Walter Guggenbuhl:
A voltage-controllable linear MOS transconductor using bias offset technique. 315-317 - Donald C. Mayer, Alfred Lee, Allan R. Kramer, Kathleen D. Miller:
High-performance CMOS/SOS circuits in SPEAR material. 318-321
Volume 25, Number 2, April 1990
- Klaus D. Müller-Glaser, Jürgen Bortolazzi:
An approach to computer-aided specification. 335-345 - Allen R. Barlow, Kaoru Takasuka, Yasunori Nambu, Toshio Adachi, Jun-Ichi Konno, Mineo Nishimoto, Shiro Suzuki, Kenji Nemoto, Kohji Takashima:
An integrated switched-capacitor signal processing design system. 346-352 - Eduardo L. Acuna, James P. Dervenis, Andrew J. Pagones, Fred L. Yang, Resve A. Saleh:
Simulation techniques for mixed analog/digital circuits. 353-363 - Robert A. Heaton, Donald W. Blevins, Edward W. Davis:
A bit-serial VLSI array processing chip for image processing. 364-368 - Allan L. Fisher, Peter T. Highnam, Todd E. Rockoff:
A four-processor building block for SIMD processor arrays. 369-375 - Hiroyuki Watanabe, Wayne D. Dettloff, Kathy E. Yount:
A VLSI fuzzy logic controller with reconfigurable, cascadable architecture. 376-382 - Creigton Asato, Christoph Ditzen, Sutrdh Dholakia:
A data-path multiplier with automatic insertion of pipeline stages. 383-387 - Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu:
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. 388-395 - Jürgen Kernhof, Manfred Selzer, Michiel A. Beunder, Bernd Hoefflinger, Bernd Laquai, Inge Schindler:
Mixed static and domino logic on the CMOS gate forest. 396-402 - Takehisa Hayashi, Toshio Doi, Mitsuo Asai, Kenichi Ishibashi, Shoji Shukuri, Atsuo Watanabe, Makoto Suzuki:
The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits. 403-409 - Katsumoto Soejima, Akira Shida, Hiroshi Koga, Junnichi Ukai, Hiroshi Sata, Masaki Hirata:
A BiCMOS technology with 660-MHz vertical p-n-p transistor for analog/digital ASICs. 410-416 - Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka:
A high-density NAND EEPROM with block-page programming for microcomputer applications. 417-424 - Scott C. Munroe, Duane R. Arsenault, Karl E. Thompson, Ana L. Lattes:
Programmable, four-channel, 128-sample, 40-Ms/s analog-ternary correlator. 425-430 - Mike Rebeschini, Nicholas R. van Bavel, Patrick Rakers, Robert Greene, James Caldwell, John R. Haug:
A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation. 431-440 - Fathy F. Yassa, Steven L. Garverick:
A multichannel digital demodulator for LVDT/RVDT position sensors. 441-450 - King-Wah W. Yeung, James D. Meindel:
An intelligent multiplexer/driver integrated circuit for an implantable multichannel blood flowmeter. 451-457 - Masao Akata, Yuichiro Nagataki, Kunihiro Koyabu, Kanji Mukai, Shinji Yoshida, Shegehi Morisaki, Masahiro Eda, Isamu Ueki, Toru Matsui:
A no-trimming SLIC two-chip set with coin telephone signaling facilities. 458-465 - Hidetoshi Onodera, Hiroyuki Kanbara, Keikichi Tamaru:
Operational-amplifier compilation with performance optimization. 466-473 - Marc E. Levitt, Jacob A. Abraham:
Physical design of testable VLSI: techniques and experiments. 474-481 - Mehdi Katoozi, Mani Soma:
Built-in test of CMOS state machines with realistic faults: a system perspective. 482-489 - Michel S. Nakhla:
Analysis of pulse propagation on high-speed VLSI chips. 490-494 - Masato Nagamatsu, Shigeru Tanaka, Junji Mori, Katsusi Hirano, Tatsuo Noguchi, Kazuhisa Hatanaka:
A 15-ns 32*32-b CMOS multiplier with an improved parallel structure. 494-497 - Peter M. Van Peteghem, Humberto M. Fossati, Glenn L. Rice, Sang-Yong Lee:
Design of a very linear CMOS transconductance input stage for continuous-time filters. 497-501 - Matthijs D. Pardoen, Marc G. R. Degrauwe:
A rail-to-rail input/output CMOS power amplifier. 501-504 - Mustafa Karaman, Levent Onural, Abdullah Atalar:
Design and implementation of a general-purpose median filter unit in CMOS VLSI. 505-513 - Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
A built-in self-test algorithm for row/column pattern sensitive faults in RAMs. 514-524 - Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada:
Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM. 525-530 - Igor De Rycke, André Van Calster, Jan Vanfleteren, Johan de Baets, Jan Doutreloigne, Herbert De Smet, Peter Vetter:
2-MHz clocked LCD drivers on glass. 531-538 - Shoichi Shimizu, Kunio Yoshihara, Toshiyuki Terada, Kenji Ishida, Yoshiaki Kitaura, Chiaki Takubo:
An ECL-compatible GaAs SCFL design method. 539-545 - Liciano Tomasini, Alberto Gola, Rinaldo Castello:
A fully differential CMOS line driver for ISDN. 546-554 - Ting-Ping Liu, Robert G. Meyer:
A 250-MHz monolithic voltage-controlled oscillator with low temperature coefficient. 555-561 - Robert H. Walden, Adele E. Schmitz, Allan R. Kramer, Lawrence E. Larson, John Pasiecznik:
A deep-submicrometer analog-to-digital converter using focused-ion-beam implants. 562-571 - Wen Fang:
Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits. 572-583 - Takayasu Sakurai, A. Richard Newton:
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. 584-594 - Krishna Shenai:
Effect of gate resistance on high-frequency power switching efficiencies of advanced power MOSFETs. 595-601 - Michael J. McNutt, Reed B. Maattson, Ahn N. Vu:
Schottky-barrier infrared focal plane arrays with novel readout structures. 602-608 - Michiel Steyaert, Willy Sansen:
Low-power monolithic signal-conditioning system. 609-612 - Arie Arbel, Benjamin Sabbah, Y. Shoham:
The complementary Darlington-a novel current source for ICs. 612-613 - Qin Huang, Gehan A. J. Amaratunga, Ekkanath Madathil Sankara Narayanan, William I. Milne:
Static CMOS latch-up considerations in HVIC design. 613-616 - L. Dunlop:
An efficient MOSFET current model for analog circuit simulation-subthreshold to strong inversion. 616-619 - Denis J. F. Doyle, William A. Lane:
Improved bipolar transistor performance in CMOS by novel use of parasitic collector resistance. 619-623 - Durgamadhab Misra:
A novel CMOS magnetic field sensor array. 623-625
Volume 25, Number 3, June 1990
- Stephen D. Levy, Paul J. Hurst, Peicheng Ju, John M. Huggins, Christopher R. Cole:
A single-chip 5-V 2400-b/s modem. 632-643 - Johann J. J. Haspeslagh, Willy M. C. Sansen:
A total solution for a 9600-b/s modem transmitter chip. 644-652 - Kazunori Tsugaru, Yasuhiuro Sugimoto, Makoto Noda, Takao Ito, Yoshito Suwa:
A single-power-supply 10-b video BiCMOS sample-and-hold IC. 653-659 - João C. Vital, José E. Franca, Franco Maloberti:
Integrated mixed-mode digital-analog filter converters. 660-668 - Rinaldo Castello, Alberto G. Grassi, Stefano Donati:
A 500-nA sixth-order bandpass SC filter. 669-676 - Frans A. C. M. Schoofs, Carmen N. G. Dupont:
A 700-V interface IC for power bridge circuits. 677-683 - Ludwig G. A. Callewaert, Willy M. C. Sansen:
Class AB CMOS amplifiers with high efficiency. 684-691 - Jack G. Sneep, Chris J. M. Verhoeven:
A new low-noise 100-MHz balanced relaxation oscillator. 692-698 - George Wegmann, Eric A. Vittoz:
Analysis and improvements of accurate dynamic current mirrors. 699-706 - Georges G. E. Gielen, Herman C. C. Walscharts, Willy M. C. Sansen:
Analog circuit design optimization based on symbolic simulation and simulated annealing. 707-713 - Lars Philipson:
Multilevel design and verification of hardware/software systems. 714-719 - Eddy Blokken, Hans De Keulenaer, Francky Catthoor, Hugo J. De Man:
A flexible module library for custom DSP applications in a multiprocessor environment. 720-729 - Christophe Joanblanq, Patrice Senn, Marie-Jean Colaitis:
A 54-MHz CMOS programmable video signal processor for HDTV applications. 730-734 - Winfried Kamp, Ronald Kuenemund, Heinz Soldner, Reinhold Hofer:
Programmable 2D linear filter for video applications. 735-740 - Doris Schmitt-Landsiedel, Bernhard Hoppe, Gerd Neuendorf, Maria Wurm, Josef Winnerl:
Pipelined architecture for fast CMOS buffer RAMs. 741-747 - Andre M. Vandemeulebroecke, Etienne Vanzieleghem, Tony Denayer, Paul G. A. Jespers:
A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor. 748-756 - François Krummenacher, Gilles van Ruymbeke:
Integrated selectivity for narrow-band FM IF systems. 757-760 - H. Herrmann, Rudolf Koch:
A 1.544-Mb/s CMOS line driver for a 22.8- Omega load. 760-763 - Jürgen Hauenschild, Hans-Martin Rein:
Influence of transmission-line interconnections between gigabit-per-second ICs on time jitter and instabilities. 763-766 - David Renshaw, Choon How Lau:
Race-free clocking of CMOS pipelines using a single global clock. 766-769 - Takashi Hotta, Tadaaki Bandoh, Atsuo Hotta, Tetsuo Nakano, Shoji Iwamoto, Shigemi Adachi:
A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library. 770-777 - Kiyoo Itoh:
Trends in megabit DRAM circuit design. 778-789 - Naresh R. Shanbhag, Dipankar Nagchoudhuri, Raymond E. Siferd, Gangaikondan S. Visweswaran:
Quaternary logic circuits in 2- mu m CMOS technology. 790-799 - Niraj K. Jha, Qiao Tong:
Testing of multiple-output domino logic (MODL) CMOS circuits. 800-805 - Nick Kanopoulos, Nagesh Vasanthavada:
Testing of differential cascade voltage switch (DCVS) circuits. 806-813 - Côme Rozon, Hussein T. Mouftah:
Realization of a three-valued logic built-in testing structure. 814-820 - Lih-Jiuan Pu, Yannis P. Tsividis:
Transistor-only frequency-selective circuits. 821-832 - Zhongyuan Chang, Willy M. C. Sansen:
Low-noise, low-distortion CMOS AM wide-band amplifiers matching a capacitive source. 833-840 - Ho-Jun Song, Choong-Ki Kim:
An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers. 841-848 - Paul W. Hollis, John J. Paulos:
Artificial neural networks using MOS analog multipliers. 849-855 - Tuan Ngo, Rick Hester:
Op amp combining precision, high speed, and high output current drive for +or-5-V power supply operation. 856-862 - Hyun J. Shin:
Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits. 863-865 - Pinaki Mazumder, Janak H. Patel, Jacob A. Abraham:
A reconfigurable parallel signature analyzer for concurrent error correction in DRAM. 866-870 - Kenneth J. Schultz, Robert J. Francis, Kenneth C. Smith:
Ganged CMOS: trading standby power for speed. 870-873 - Rochit Rajsuman:
Implementation of switch network logic in SOI. 874-877 - Qiao Tong, Niraj K. Jha:
Testing of zipper CMOS logic circuits. 877-880 - Khayrollah Hadidi, Vincent S. Tso, Gabor C. Temes:
An 8-b 1.3-MHz successive-approximation A/D converter. 880-885