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IEEE Journal of Solid-State Circuits, Volume 34
Volume 34, Number 1, January 1999
- Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song:
A 5-MHz IF digital FM demodulator. 3-11 - Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino:
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. 12-17 - Kenichi Ohhata, Toru Masuda, Kazuo Imai, Ryoji Takeyari, Katsuyoshi Washio:
A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links. 18-24 - Mohammad Madihian, Tomislav Drenski, Laurent Desclos, Hiroshi Yoshida, Hiroshi Hirabayashi, Tohru Yamazaki:
A 5-GHz-band multifunctional BiCMOS transceiver chip for GMSK modulation wireless systems. 25-32 - Akira Ohta, Norio Higashisaka, Tetsuya Heima, Takayuki Hisaka, Hirofumi Nakano, Ryuji Ohmura, Tadashi Takagi, Noriyuki Tanino:
A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure. 33-41 - Jean Michel Daga, Daniel Auvergne:
A comprehensive delay macro modeling for submicrometer CMOS logics. 42-55 - Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. 56-67 - Yuh-Kuang Tseng, Chung-Yu Wu:
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications. 68-79 - Mohamed Nekili, Yvon Savaria, Guy Bois:
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. 80-84 - Nick Lindert, Toshihiro Sugii, Stephen Tang, Chenming Hu:
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages. 85-89 - Vincent Wing-Yun Sit, Chiu-Sing Choy, Cheong-Fat Chan:
A four-phase handshaking asynchronous static RAM design for self-timed systems. 90-96 - Joao Navarro Soares, Wilhelmus A. M. Van Noije:
A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). 97-102 - Steve H. Jen, Bing J. Sheu, Yoondong Park:
A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's. 103-106 - Barbaros Sekerkiran:
A compact rail-to-rail output stage for CMOS operational amplifiers. 107-110 - K. R. Lakshmikumar, J. Anidjar:
A low-voltage line driver for digital signaling interface. 111-115 - Pang-Cheng Yu, Jiin-Chuan Wu:
A class-B output buffer for flat-panel-display column driver. 116-119 - Joaquín Portilla
, Héctor García, Eduardo Artal
:
High power-added efficiency MMIC amplifier for 2.4 GHz wireless communications. 120-123 - Robert H. Caverly:
Linear and nonlinear characteristics of the silicon CMOS monolithic 50-Ω microwave and RF control element. 124-126 - Loke Kun Tan, Jeffrey S. Putnam, Fang Lu, Lionel J. D'Luna, Dean W. Mueller, Kenneth R. Kindsfater, Kelly B. Cameron, Robindra B. Joshi, Robert A. Hawley, Henry Samueli:
Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder". 127 - Clemens M. Hammerschmied, Qiuting Huang:
Addition to "Design and Implementation of an Untrimmed MOSFET-Only 10-bit A/D Converter with -79-dB THD". 127
Volume 34, Number 3, March 1999
- Behzad Razavi:
CMOS technology characterization for analog and RF design. 268-276 - Tajinder Manku:
Microwave CMOS-device physics and design. 277-285 - Joo Leong (Julian) Tham, Mihai A. Margarit, Bernd Prégardier, Christopher D. Hull, Rahul Magoon, Frank Carr:
A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication. 286-291 - Qiuting Huang, Paolo Orsatti, Francesco Piazza:
GSM transceiver front-end circuits in 0.25-μm CMOS. 292-303 - Ravindranath Naiknaware, Terri S. Fiez:
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. 304-303 - Ravindranath Naiknaware, Terri S. Fiez:
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. 304-317 - Benoit Dufort, Gordon W. Roberts:
On-chip analog signal generation for mixed-signal built-in self-test. 318-330 - Tao Shui, Richard Schreier, Forrest Hudson:
Mismatch shaping for a current-mode multibit delta-sigma DAC. 331-338 - Hiok-Tiaq Ng, Ramsin M. Ziazadeh, David J. Allstot:
A multistage amplifier technique with embedded frequency compensation. 339-347 - David X. D. Yang, Boyd Fowler, Abbas El Gama:
A Nyquist-rate pixel-level ADC for CMOS image sensors. 348-356 - Hiroshi Iwai:
CMOS technology-year 2010 and beyond. 357-366 - Jone F. Chen, Jiang Tao, Peng Fang, Chenming Hu:
Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates. 367-371 - Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, Hisamitsu Suzuki:
A direct-skew-detect synchronous mirror delay for application-specific integrated circuits. 372-379 - Bevan M. Baas:
A low-power, high-performance, 1024-point FFT processor. 380-387 - Wolfgang Wilhelm:
A new scalable VLSI architecture for Reed-Solomon decoders. 388-396 - Byoung-Woon Kim, Jin-Hyuk Yang, Chan-Soo Hwang, Young-Su Kwon, Keun-Moo Lee, In-Hyoung Kim, Yong-Hoon Lee, Chong-Min Kyung:
MDSP-II: a 16-bit DSP with mobile communication accelerator. 397-404 - Hema Kapadia, Luca Benini, Giovanni De Micheli:
Reducing switching activity on datapath buses with control-signal gating. 405-414 - Christian Menolfi, Qiuting Huang:
A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset. 415-420
Volume 34, Number 4, April 1999
- Loai Louis, John Abcarius, Gordon W. Roberts:
An eighth-order bandpass ΔΣ modulator for A/D conversion in digital radio. 423-431 - Sunny S. W. Chan, Philip C. H. Chan:
A resistance-variation-tolerant constant-power heating circuit for integrated sensor applications. 432-439 - Clark T.-C. Nguyen, Roger T. Howe:
An integrated CMOS micromechanical resonator high-Q oscillator. 440-455 - Mark Lemkin, Bernhard E. Boser:
A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics. 456-468 - Jeong-Woo Lee, Dong-Jin Min, Jiyoun Kim, Wonchan Kim:
A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique. 469-475 - Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka:
New three-dimensional memory array architecture for future ultrahigh-density DRAM. 476-483 - Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, Wonchan Kim:
An analog synchronous mirror delay for high-speed DRAM application. 484-493 - Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. 494-501 - Kazuya Yamamoto, Takao Moriwaki, Takayuki Fujii, Jun Otsuji, Miyo Miyashita, Yukio Miyazaki, Kazuo Nishitani:
A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications. 502-512 - David W. Boerstler:
A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz. 513-519 - Gu-Yeon Wei, Mark Horowitz:
A fully digital, energy-efficient, adaptive power-supply regulator. 520-528 - Jae-Yoon Sim, Young-Soo Sohn, Seung-Chan Heo, Hong-June Park, Soo-In Cho:
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. 529-535 - Vladimir Stojanovic
, Vojin G. Oklobdzija:
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. 536-548 - M. Omair Ahmad, Shenghong Wang:
A design and implementation of fully programmable switched-current IIR filters. 549-553 - Shen-Iuan Liu, Jiunn-Hwa Lee, Hen-Wai Tsao
:
Low-power clock-deskew buffer for high-speed digital circuits. 554-558 - Kamel Ayadi:
High-speed, highly sensitive OEIC using clocked vertical BJT's photoDarlington in CMOS technology. 559-564 - Feng Lin, Jason Miller, Aaron Schoenfeld, Manny Ma, R. Jacob Baker:
A register-controlled symmetrical DLL for double-data-rate DRAM. 565-568
Volume 34, Number 5, May 1999
- William Bidermann, Masao Taguchi:
Guest Editorial. 571-572 - Behzad Razavi:
A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications. 573-579 - Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. 580-585 - Chan-Hong Park, Beomsup Kim:
A low-noise, 900-MHz VCO in 0.6-μm CMOS. 586-591 - Michael Q. Le, Paul J. Hurst, Kenneth C. Dyer:
An analog DFE for disk drives using a mixed-signal integrator. 592-598 - Andrew M. Abo, Paul R. Gray:
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. 599-606 - Katayoun Falakshahi, Chih-Kong Ken Yang, Bruce A. Wooley:
A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation. 607-615 - Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong:
A 1-GHz logic circuit family with sense amplifiers. 616-622 - Krishnamurthy Soumyanath, Shekhar Borkar, Chunyan Zhou, Bradley A. Bloechel:
Accurate on-chip interconnect evaluation: a time-domain technique. 623-631 - Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz:
A portable digital DLL for high-speed CMOS interface circuits. 632-644 - Changhyun Kim, Kye-Hyun Kyung, W.-P. Jeong, J.-S. Kim, Byung-Sik Moon, Joon-Wan Chai, S.-M. Yim, Jung-Hwan Choi, K.-H. Han, C.-J. Park, Hong-Sun Hwang, H. Choi, Sung-Burn Cho, Clemenz L. Portmann, Soo-In Cho:
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. 645-652 - Takashi Sato
, Yoji Nishio, Toshio Sugano, Yoshinobu Nakagome:
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. 653-660 - Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima
, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada:
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. 661-669 - Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa
, Shigeru Atsumi, Koji Sakui:
A CMOS bandgap reference circuit with sub-1-V operation. 670-674 - Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui:
A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. 675-684 - Hiroaki Ikeda, Hidemori Inukai:
High-speed DRAM architecture development. 685-692 - Thucydides Xanthopoulos, Anantha P. Chandrakasan:
A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity. 693-703 - Tarek Lulé, Bernd Schneider, Markus Böhm:
Design and fabrication of a high-dynamic-range image sensor in TFA technology. 704-711 - Fabian Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Raymond A. Heald, Gin Yee:
A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. 712-716 - Ali Hajimiri
, Thomas H. Lee:
Design issues in CMOS differential LC oscillators. 717-724 - Caesar S. Wong:
A 3-V GSM baseband transmitter. 725-730
Volume 34, Number 6, June 1999
- Hirokazu Yoshizawa, Yunteng Huang, Paul F. Ferguson Jr., Gabor C. Temes:
MOSFET-only switched-capacitor circuits in digital CMOS technology. 734-747 - Fernando Medeiro
, Belén Pérez-Verdú
, Ángel Rodríguez-Vázquez
:
A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology. 748-760 - Mihai A. Margarit, Joo Leong Tham, Robert G. Meyer, M. Jamal Deen
:
A low-noise, low-power VCO with automatic amplitude control for wireless applications. 761-771 - Manolis Terrovitis, Robert G. Meyer:
Noise in current-commutating CMOS mixers. 772-783 - Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V, 1.8-GHz BJT phase-locked loop. 784-789 - Ali Hajimiri
, Sotirios Limotyrakis, Thomas H. Lee:
Jitter and phase noise in ring oscillators. 790-804 - Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino:
A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. 805-812 - Hamid R. Rategh, Thomas H. Lee:
Superharmonic injection-locked frequency dividers. 813-821 - Akira Nakada, Tadashi Shibata, Masahiro Konda, Tatsuo Morimoto, Tadahiro Ohmi:
A fully parallel vector-quantization processor for real-time motion-picture compression. 822-830 - Jeffrey C. Gealow
, Charles G. Sodini:
A pixel-parallel image processor using logic pitch-matched to dynamic memory. 831-839 - Kees van Berkel, Charles E. Molnar:
Beware the three-way arbiter. 840-848 - Charles Dike, Edward Burton:
Miller and noise effects in a synchronizing flip-flop. 849-855 - Dong-Sun Min, Dietrich W. Langer:
Multiple twisted dataline techniques for multigigabit DRAMs. 856-865 - Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe:
A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers. 866-877 - P. J. Sullivan, B. A. Xavier, Walter H. Ku:
Doubly balanced dual-gate CMOS mixer. 878-881 - Asad A. Abidi, John C. Leete:
De-embedding the noise figure of differential amplifiers. 882-885 - R. Schmid, Thomas F. Meister, Mirjana Rest, Hans-Martin Rein:
SiGe driver circuit with high output amplitude operating up to 23 Gb/s. 886-891 - Andrea Boni, Carlo Morandi, Silvia Padoan:
A 2.5-V BiCMOS comparator with current-mode interpolation. 892-897 - Joonho Lim, Dong-Gyu Kim, Soo-Ik Chae:
A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. 898-903 - Joonbae Park, Jeongho Lee, Wonchan Kim:
Current sensing differential logic: a CMOS logic for high reliability and flexibility. 904-908
Volume 34, Number 7, July 1999
- Iuri Mehr, Declan Dalton:
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications. 912-920 - Dan B. Kasha, Wai L. Lee, Axel Thomsen:
A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing. 921-926 - Yves Geerts, Augusto Manuel Marques, Michel S. J. Steyaert
, Willy Sansen:
A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. 927-936 - Christopher F. Edwards, William Redman-White, Mark Bracey, Bernard M. Tenbroek, Michael S. L. Lee, Michael J. Uren
:
A multibit ΣΔ modulator in floating-body SOS/SOI CMOS for extreme radiation environments. 937-948 - Anne-Johan Annema
:
Low-power bandgap references featuring DTMOSTs. 949-955 - John van den Homberg:
A universal 0.03-mm2 one-pin crystal oscillator in CMOS. 956-961 - King-Chun Tsai, Paul R. Gray:
A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications. 962-970 - Mark Ingels, Michel S. J. Steyaert
:
A 1-Gb/s, 0.7-μm CM+ OS optical receiver with full rail-to-rail output swing. 971-977 - Stefan Jung, Roland Thewes, Thomas Scheiter, Karl F. Goser, Werner Weber:
A low-power and high-performance CMOS fingerprint sensing and encoding architecture. 978-984 - Ronan A. R. van der Zee
, Ed A. J. M. van Tuijl:
A power-efficient audio amplifier combining switching and linear techniques. 985-991 - Atsushi Mohri, Akira Yamada, Y. Yoshida, Hisakazu Sato, Hidehiro Takata, K. Nakakimura, M. Hashizume, Y. Shimotsuma, K. Tsuchihashi:
A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor. 992-1000 - L. Kiss, K. Adriaensen, C. Gendarme, E. Hanssens, M. Huysmans, F. van Beylen, Hugo van de Weghe:
SACHEM, a versatile DMT-based modem transceiver for ADSL. 1001-1009 - Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina:
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. 1010-1021 - Sander L. J. Gierkink, Eric A. M. Klumperink, Arnoud P. van der Wel, Gian Hoogzaad, Ed A. J. M. van Tuijl, Bram Nauta
:
Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators. 1022-1025 - John Clouser, Mark Matson, R. Badeau, R. Dupcak, Sridhar Samudrala, Randy L. Allmon, N. Fairbanks:
A 600-MHz superscalar floating-point processor. 1026-1029
Volume 34, Number 8, August 1999
- Avanindra Madisetti, Alan Y. Kwentus, Alan N. Willson Jr.:
A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range. 1034-1043 - Joseph N. Babanezhad:
A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driver for Ethernet and fast Ethernet networking applications. 1044-1050 - Akira Nagayama, Masatoyo Nishibe, Takayuki Inaoka, Nobuhiro Mineshima:
Low-insertion-loss DP3T MMIC switch for dual-band cellular phones. 1051-1055 - K. Nagaraj, F. Chen, T. R. Viswanathan:
Efficient 6-bit A/D converter using a 1-bit folding front end. 1056-1062 - Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee:
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit. 1063-1073 - Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama:
Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS. 1074-1083 - Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. 1084-1090 - Toru Tanzawa
, Shigeru Atsumi:
Optimization of word-line booster circuits for low-voltage flash memories. 1091-1098 - Aaron Partridge, J. Kurth Reynolds, John D. Grade, Bart J. Kane, Nadim I. Maluf, Gregory T. A. Kovacs, Thomas W. Kenny:
An integrated controller for tunnel sensors. 1099-1107 - Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel:
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. 1108-1117 - Masoud Zargari, Justin Leung, S. Simon Wong, Bruce A. Wooley:
A BiCMOS active substrate probe-card technology for digital testing. 1118-1135 - Michael Schröter, Hans-Martin Rein, Winfried Rabe, Reinhard Reimann, Hans-Joachim Wassener, Andreas Koldehoff:
Physics- and process-based bipolar transistor modeling for integrated circuit design. 1136-1149 - Saska Lindfors, Jarkko Jussila, Kari Halonen, Lauri Siren:
A 3-V continuous-time filter with on-chip tuning for IS-95. 1150-1154 - Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu:
A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC.