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IEEE Journal of Solid-State Circuits, Volume 47
Volume 47, Number 1, January 2012
- Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu:
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. 3-7 - Vivienne Sze, Anantha P. Chandrakasan:
A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding. 8-22 - Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS. 23-34 - Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28 nm 0.6 V Low Power DSP for Mobile Applications. 35-46 - Niklas Lotze, Yiannos Manoli:
A 62 mV 0.13 µ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic. 47-60 - Shyuan Liao, Yen-Shuo Chang, Chia-Hsin Wu, Hung-Chieh Tsai, Hsin-Hua Chen, Min Chen, Ching-Wen Hsueh, Jian-Bang Lin, Den-Kai Juang, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chih-Heng Shih, Barry Hong, Heng-Ruey Hsu, Chih-Yuan Wang, Meng-Shiang Lin, Wei-Hsiang Tseng, Che-Hsiung Yang, Lawrence Chen Lee, Ting-Jyun Jheng, Wen-Wei Yang, Ming-Yang Chao, Jyh-Shin Pan:
A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router. 61-74 - Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara:
A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology. 75-84 - Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi:
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. 85-96 - Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic:
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. 97-106 - Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Joo-Sun Choi, Young-Hyun Jun:
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. 107-116 - Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Mau-Chung Frank Chang:
An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling. 117-130 - Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. 131-140 - Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan:
A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin. 141-150 - James D. Warnock, Yiu-Hing Chan, Sean M. Carey, Huajun Wen, Patrick J. Meaney, Guenter Gerwig, Howard H. Smith, Yuen H. Chan, John Davis, Paul Bunce, Antonio Pelella, Daniel Rodko, Pradip Patel, Thomas Strach, Doug Malone, Frank Malgioglio, José Neves, David L. Rude, William V. Huott:
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System. 151-163 - Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh:
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. 164-176 - Reid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley O. Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw:
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers. 177-193 - Marcelo Yuffe, Moty Mehalel, Ernest Knoll, Joseph Shor, Tsvika Kurts, Eran Altshuler, Eyal Fayneh, Kosta Luria, Michael Zelikson:
A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor. 194-205 - Wonyoung Kim, David M. Brooks, Gu-Yeon Wei:
A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS. 206-219 - Denis Foley, Pankaj Bansal, Don Cherepacha, Robert Wasmuth, Aswin Gunasekar, Srinivasa Rao Gutta, Ajay Naini:
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices. 220-231 - Rikky Muller, Simone Gambini, Jan M. Rabaey:
A 0.013 mm2, 5 µW , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply. 232-243 - Emilia Noorsal, Kriangkrai Sooksood, Hongcheng Xu, Ralf Hornig, Joachim Becker, Maurits Ortmanns:
A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants. 244-256 - Albert Wang, Alyosha C. Molnar:
A Light-Field Image Sensor in 180 nm CMOS. 257-271 - Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito:
A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC. 272-283 - Kris Myny, Erik van Veenendaal, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil. 284-291 - Tarek Zaki, Frederik Ante, Ute Zschieschang, Joerg Butschke, Florian Letzkus, Harald Richter, Hagen Klauk, Joachim N. Burghartz:
A 3.3 V 6-Bit 100 kS/s Current-Steering Digital-to-Analog Converter Using Organic P-Type Thin-Film Transistors on Glass. 292-300 - Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier. 301-309 - Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Hoi-Jun Yoo:
A 0.24-nJ/b Wireless Body-Area-Network Transceiver With Scalable Double-FSK Modulation. 310-322 - Seulki Lee, Long Yan, Taehwan Roh, Sunjoo Hong, Hoi-Jun Yoo:
A 75 µ W Real-Time Scalable Body Area Network Controller and a 25 µW ExG Sensor IC for Compact Sleep Monitoring Applications. 323-334 - Yu-Te Liao, Huanfen Yao, Andrew Lingley, Babak A. Parviz, Brian P. Otis:
A 3-µW CMOS Glucose Sensor for Wireless Contact-Lens Tear Glucose Monitoring. 335-344 - Alexander V. Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Solomon Assefa, Fuad E. Doany, Min Yang, Joris Van Campenhout, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov:
Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers. 345-354
Volume 47, Number 2, February 2012
- Sang-Young Kim, Gabriel M. Rebeiz:
A Low-Power BiCMOS 4-Element Phased Array Receiver for 76-84 GHz Radars and Communication Systems. 359-367 - Joohwa Kim, James F. Buckwalter:
A Switchless, Q-Band Bidirectional Transceiver in 0.12-µm SiGe BiCMOS Technology. 368-380 - Diptendu Ghosh, Ranjit Gharpurey:
A Power-Efficient Receiver Architecture Employing Bias-Current-Shared RF and Baseband With Merged Supply Voltage Domains and 1/f Noise Reduction. 381-391 - Donggu Im, Hongteuk Kim, Kwyro Lee:
A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts. 392-406 - Danilo Manstretta:
A Broadband Low-Power Low-Noise Active Balun With Second-Order Distortion Cancellation. 407-420 - Yuyu Chang, John C. Leete, Zhimin Zhou, Morteza Vadipour, Yin-Ting Chang, Hooman Darabi:
A Differential Digitally Controlled Crystal Oscillator With a 14-Bit Tuning Resolution and Sine Wave Outputs for Cellular Applications. 421-434 - Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno:
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. 435-443 - Wei-Te Lin, Tai-Haur Kuo:
A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection. 444-453 - Youngkil Choi, Wonho Tak, Younghyun Yoon, Jeongjin Roh, Sunwoo Kwon, Jinseok Koh:
A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup. 454-463 - Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
A 21 nV/√ Hz Chopper-Stabilized Multi-Path Current-Feedback Instrumentation Amplifier With 2 µ V Offset. 464-475 - Chenling Huang, Shantanu Chakrabartty:
An Asynchronous Analog Self-Powered CMOS Sensor-Data-Logger With a 13.56 MHz RF Programming Interface. 476-489 - Daniel Fernández, Luís Martínez-Alvarado, Jordi Madrenas:
A Translinear, Log-Domain FPAA on Standard CMOS Technology. 490-503 - Luis A. Camuñas-Mesa, Carlos Zamarreño-Ramos, Alejandro Linares-Barranco, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. 504-517 - Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim:
MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization. 518-535 - Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii:
An Embedded DRAM Technology for High-Performance NAND Flash Memories. 536-546 - Ki Chul Chun, Pulkit Jain, Tae-Ho Kim, Chris H. Kim:
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. 547-559 - Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang:
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. 560-573 - Charalambos M. Andreou, Savvas Koudounas, Julius Georgiou:
A Novel Wide-Temperature-Range, 3.9 ppm/°C CMOS Bandgap Reference Circuit. 574-581
Volume 47, Number 3, March 2012
- Simone Gambini, John Crossley, Elad Alon, Jan M. Rabaey:
A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects. 586-598 - Jihwan Kim, Woonyun Kim, Hamhee Jeon, Yan-Yu Huang, Youngchang Yoon, Hyungwook Kim, Chang-Ho Lee, Kevin T. Kornegay:
A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer. 599-614 - Joohwa Kim, James F. Buckwalter:
A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS. 615-626 - Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. 627-640 - Matthew Loh, Azita Emami-Neyestanak:
A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O. 641-651 - Mehran M. Izad, Chun-Huat Heng:
A Pulse Shaping Technique for Spur Suppression in Injection-Locked Synthesizers. 652-664 - Jaewook Shin, Hyunchol Shin:
A 1.9-3.8 GHz ΔΣ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency. 665-675 - Brandon Rumberg, David W. Graham:
A Low-Power Magnitude Detector for Analysis of Transient-Rich Signals. 676-685 - Federico Guanziroli, Rossella Bassoli, Carlo Crippa, Daniele Devecchi, Germano Nicollini:
A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction. 686-698 - Matteo Crotti, Ivan Rech, Massimo Ghioni:
Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting. 699-708 - Fridolin Michel, Michiel Steyaert:
A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS. 709-721 - Zhenglin Yang, Libin Yao, Yong Lian:
A 0.5-V 35-µW 85-dB DR Double-Sampled ΔΣ Modulator for Audio Applications. 722-735 - Young Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim:
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS. 736-743 - Fred Chen, Anantha P. Chandrakasan, Vladimir Stojanovic:
Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors. 744-756 - Chia-Hsiang Yang, Tsung-Han Yu, Dejan Markovic:
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example. 757-768 - Kwen-Siong Chong, Kok-Leong Chang, Bah-Hwee Gwee, Joseph S. Chang:
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors. 769-780
Volume 47, Number 4, April 2012
- Makoto Nagata, Vivek De:
Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. 795-796 - Yu-Chi Su, Keng-Yen Huang, Tse-Wei Chen, Yi-Min Tsai, Shao-Yi Chien, Liang-Gee Chen:
A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications. 797-809 - Shinichiro Uemura, Yukio Hiraoka, Takayuki Kai, Shiro Dosho:
Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. 810-816 - Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. 817-831 - Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno:
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. 832-840 - Mohammad K. Al-Ghamdi, Anas A. Hamoui:
A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a ΔΣ-Modulator Controller With a Scalable Sampling Frequency. 841-851 - Tzu-Chi Huang, Chun-Yu Hsieh, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Ming-Wei Lee:
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control. 852-862 - John F. Bulzacchelli, Zeynep Toprak Deniz, Todd M. Rasmus, Joseph A. Iadanza, William L. Bucossi, Seongwon Kim, Rafael Blanco, Carrie E. Cox, Mohak Chhabra, Christopher D. LeBlanc, Christian L. Trudeau, Daniel J. Friedman:
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. 863-874 - Dong-Woo Jee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC. 875-883 - Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman:
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. 884-896 - Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf:
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. 897-910 - Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. 911-925 - Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. 926-937 - E-Hung Chen, Ramy Yousry, Chih-Kong Ken Yang:
Power Optimized ADC-Based Serial Link Receiver. 938-951 - Chintan Thakkar, Lingkai Kong, Kwangmo Jung, Antoine Frappé, Elad Alon:
A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS. 952-968 - Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi:
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM. 969-980 - Chulbum Kim, Jinho Ryu, Tae-Sung Lee, Hyunggon Kim, Jaewoo Lim, Jaeyong Jeong, Seonghwan Seo, Hongsoo Jeon, Bokeun Kim, Inyoul Lee, Dooseop Lee, Pansuk Kwak, Seongsoon Cho, Yongsik Yim, Changhyun Cho, Woopyo Jeong, Kwang-Il Park, Jin-Man Han, Duheon Song, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun:
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. 981-989 - Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. 990-1002 - Frank Van de Sande, Nico Lugil, Filip Demarsin, Zeger Hendrix, Alvin Andries, Peter Brandt, William Anklam, Jeffery S. Patterson, Brian Miller, Michael Rytting, Mike Whaley, Bob Jewett, Jacky Liu, Jake Wegman, Ken Poulton:
A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz fT BiCMOS Process. 1003-1012 - Chun-Ying Chen, Jiangfeng Wu, Juo-Jung Hung, Tianwei Li, Wenbo Liu, Wei-Ta Shih:
A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm2 and 500 mW in 40 nm Digital CMOS. 1013-1021 - Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. 1022-1030 - Gordon Wan, Xiangli Li, Gennadiy Agranov, Marc Levoy, Mark Horowitz:
CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography. 1031-1042 - Hua Gao, Ross M. Walker, Paul Nuyujukian, Kofi A. A. Makinwa, Krishna V. Shenoy, Boris Murmann, Teresa H. Meng:
HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 µm CMOS. 1043-1055 - Paul Peng Liu, Karl Skucha, Yida Duan, Mischa Megens, Jungkyu Kim, Igor I. Izyumin, Simone Gambini, Bernhard E. Boser:
Magnetic Relaxation Detector for Microbead Labels. 1056-1064
Volume 47, Number 5, May 2012
- Un-Ku Moon:
New Associate Editors. 1071-1072 - Georg Böck:
Overview for the Special Section on the 2011 Radio Frequency Integrated Circuits (RFIC) Symposium. 1073-1074 - Laurent Negre, David Roy, Florian Cacho, Patrick Scheer, Sebastien Jan, Samuel Boret, Daniel Gloria, Gérard Ghibaudo:
Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses. 1075-1083 - Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi:
A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems. 1084-1093 - François Belmas, Frédéric Hameau, Jean-Michel Fournier:
A Low Power Inductorless LNA With Double Gm Enhancement in 130 nm CMOS. 1094-1103 - Toshifumi Nakatani, Jeremy Rode, Donald F. Kimball, Lawrence E. Larson, Peter M. Asbeck:
Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications. 1104-1112 - Debopriyo Chowdhury, Siva V. Thyagarajan, Lu Ye, Elad Alon, Ali M. Niknejad:
A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters. 1113-1122 - Ward S. Titus, John G. Kenney:
A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs. 1123-1130 - Jianhua Lu, Ning-Yi Wang, Mau-Chung Frank Chang:
A Compact and Low Power 5-10 GHz Quadrature Local Oscillator for Cognitive Radio Applications. 1131-1140 - Subhanshu Gupta, Daibashish Gangopadhyay, Hasnain Lakdawala, Jacques Christophe Rudell, David J. Allstot:
A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS. 1141-1153 - Jian Chen, Liang Rong, Fredrik Jonsson, Geng Yang, Li-Rong Zheng:
The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator. 1154-1164 - Heesong Seo, In Young Choi, Changjoon Park, Jehyung Yoon, Bumman Kim:
A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX. 1165-1174 - Marc Tiebout, Hans-Dieter Wohlmuth, Herbert Knapp, Raffaele Salerno, Michael Druml, Mirjana Rest, Johann Kaeferboeck, Johann Wuertele, Sherif Sayed Ahmed, Andreas Schiessl, Ralf Juenemann, Anna Zielska:
Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology. 1175-1184 - Muhammad Hassan, Lawrence E. Larson, Vincent W. Leung, Peter M. Asbeck:
A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications. 1185-1198 - Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile. 1199-1208 - Jing Guo, George Jie Yuan, Jiageng Huang, Jessica Ka-Yan Law, Chi-Kong Yeung, Mansun Chan:
32.9 nV/rt Hz - 60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC. 1209-1220 - Xicheng Jiang, Jungwoo Song, Jianlong Chen, Vinay Chandrasekhar, Sherif Galal, Felix Y. L. Cheung, Darwin Cheung, Todd Brooks:
A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 µm CMOS. 1221-1231 - Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda:
A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS. 1232-1241 - Yingchieh Ho, Chauchin Su:
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters. 1242-1251 - Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. 1252-1260
Volume 47, Number 6, 2012
- Takahiro Nakamura, Toru Masuda, Katsuyoshi Washio, Hiroshi Kondoh:
A Push-Push VCO With 13.9-GHz Wide Tuning Range Using Loop-Ground Transmission Line for Full-Band 60-GHz Transceiver. 1267-1277 - Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio:
Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators. 1278-1294