default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Journal of Solid-State Circuits, Volume 51
Volume 51, Number 1, January 2016
- Edith Beigné
, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe:
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. 3-7 - Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. 8-17 - Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. 18-30 - James Myers, Anand Savanth, Rohan Gaddh, David Howard, Pranay Prabhat, David Flynn:
A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator. 31-44 - Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Seongwook Park, Kyuho Jason Lee, Youchang Kim, Hoi-Jun Yoo:
A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses. 45-55 - Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang, Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen:
A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications. 56-67 - Fengbo Ren, Dejan Markovic:
A Configurable 12-237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals. 68-78 - Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa:
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. 79-91 - William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family. 92-104 - Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox:
Carrizo: A High Performance, Energy Efficient 28 nm APU. 105-116 - Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. 117-129 - Jaehyuk Choi, Jungsoon Shin, Dongwu Kang, Du-Sik Park:
Always-On CMOS Image Sensor for Mobile and Wearable Devices. 130-140 - Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Yoshimasa Kawata, Nobukazu Teranishi, Zhuo Li, Izhal Abdul Halin, Shoji Kawahito:
A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging. 141-154 - Matteo Perenzoni, Nicola Massari, Daniele Perenzoni, Leonardo Gasparini, David Stoppa:
A 160 × 120 Pixel Analog-Counting Single-Photon Imager With Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging. 155-167 - Changbyung Park, Sungsoo Park, Kiduk Kim, Sang-Hui Park, Juwan Park, Byunghoon Kang, Yunhee Huh, Gyu-Hyeong Cho:
A Pen-Pressure-Sensitive Capacitive Touch System Using Electrically Coupled Resonance Pen. 168-176 - Ganesh K. Balachandran, Vladimir P. Petkov, Thomas Mayer, Thorsten Balslink:
A 3-Axis Gyroscope for Electronic Stability Control With Continuous Self-Test. 177-186 - Hui Jiang, Zu-yao Chang, Michiel A. P. Pertijs:
A 30 ppm < 80 nJ Ring-Down-Based Readout Circuit for Resonant Sensors. 187-195 - Mario Sako, Yoshihisa Watanabe, Takao Nakajima, Jumpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kono, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, Masahiro Kamoshida, Masatoshi Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita:
A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. 196-203 - Woopyo Jeong, Jae-Woo Im, Doo-Hyun Kim, Sangwan Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, Hyun Wook Park, Dong-Hun Kwak, Sang-Won Park, Seok-Min Yoon, Wook-Ghee Hahn, Jinho Ryu, Sang-Won Shim, Kyung-Tae Kang, Jeong-Don Ihm, In-Mo Kim, Doosub Lee, Ji-Ho Cho, Moosung Kim, Jae-hoon Jang, Sang-Won Hwang, Dae-Seok Byeon, Hyang-Ja Yang, Ki-Tae Park, Kyehyun Kyung, Jeong-Hyuk Choi:
A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. 204-212 - Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. 213-221 - Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang:
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. 222-229 - Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. 230-239 - Pieter Harpe, Hao Gao, Rainier van Dommele, Eugenio Cantatore, Arthur H. M. van Roermund:
A 0.20 mm2 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS. 240-248 - Nicolas Delorme, Christophe Le Blanc, Alessandro Dezzani, Mickael Bely, Alexandre Ferret, Simon Laminette, Jerome Roudier, Éric Colinet:
A NEMS-Array Control IC for Subattogram Mass Sensing Applications in 28 nm CMOS Technology. 249-258 - Te-Hsuen Tzeng, Chun-Yen Kuo, San-Yuan Wang, Po-Kai Huang, Yen-Ming Huang, Wei-Che Hsieh, Yu-Jie Huang, Po-Hung Kuo, Shih-An Yu, Si-Chen Lee, Yufeng Jane Tseng, Wei-Cheng Tian, Shey-Shi Lu:
A Portable Micro Gas Chromatography System for Lung Cancer Associated Volatile Organic Compound Detection. 259-272 - Yigit Mahsereci, Stefan Saller, Harald Richter, Joachim N. Burghartz:
An Ultra-Thin Flexible CMOS Stress Sensor Demonstrated on an Adaptive Robotic Gripper. 273-280 - Warren Rieutort-Louis, Tiffany Moy, Zhuo Wang, Sigurd Wagner, James C. Sturm, Naveen Verma:
A Large-Area Image Sensing and Detection System Based on Embedded Thin-Film Classifiers. 281-290 - Komail M. H. Badami, Steven Lauwereins, Wannes Meert, Marian Verhelst:
A 90 nm CMOS, 6µW Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection. 291-302 - Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno:
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. 303-309 - Hyunwoo Cho, Hyunki Kim, Minseo Kim, Jaeeun Jang, Yongsu Lee, Kyuho Jason Lee, Joonsung Bae, Hoi-Jun Yoo:
A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5µW 100 kb/s Super-Regenerative Transceiver for Body Channel Communication. 310-317
Volume 51, Number 2, February 2016
- Venumadhav Bhagavatula, Tong Zhang, Apsara Ravish Suvarna, Jacques Christophe Rudell:
An Ultra-Wideband IF Millimeter-Wave Receiver With a 20 GHz Channel Bandwidth Using Gain-Equalized Transformers. 323-331 - Iman Madadi, Massoud Tohidian, Koen Cornelissens, Patrick Vandenameele, Robert Bogdan Staszewski:
A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection. 332-347 - Giuseppe Li Puma, Christophe Carbonne:
Mitigation of Oscillator Pulling in SoCs. 348-356 - Yan-Jiun Chen, Kwuang-Han Chang, Chih-Cheng Hsieh:
A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS. 357-364 - Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. 365-377 - Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd:
A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process. 378-390 - Shinwoong Kim, Seunghwan Hong, Kapseok Chang, Hyungsik Ju, Jaewook Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC. 391-400 - Mina Kim, Seojin Choi, Taeho Seong, Jaehyouk Choi:
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells. 401-411 - Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. 412-427 - Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu:
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. 428-439 - Sagar Ray, Mona Mostafa Hella:
A 10 Gb/s Inductorless AGC Amplifier With 40 dB Linear Variable Gain Control in 0.13 µm CMOS. 440-456 - Jun-Chau Chien, Ali M. Niknejad:
Oscillator-Based Reactance Sensors With Injection Locking for High-Throughput Flow Cytometry Using Microwave Dielectric Spectroscopy. 457-472 - Walker J. Turner, Rizwan Bashirullah:
A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring. 473-483 - JongKwan Choi, Jae-Myoung Kim, Gunpil Hwang, Jaehyeok Yang, MinGyu Choi, Hyeon-Min Bae:
Time-Divided Spread-Spectrum Code-Based 400 fW-Detectable Multichannel fNIRS IC for Portable Functional Brain Imaging. 484-495 - Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. 496-508 - Dongmin Yoon, Tae-Kwang Jang, Dennis Sylvester, David T. Blaauw:
A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks. 509-522 - Po-Hung Chen, Chung-Shiang Wu, Kai-Chun Lin:
A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting. 523-532 - Min Tan, Wing-Hung Ki:
An Efficiency-Enhanced Hybrid Supply Modulator With Single-Capacitor Current-Integration Control. 533-542 - Suyoung Bang, David T. Blaauw, Dennis Sylvester:
A Successive-Approximation Switched-Capacitor DC-DC Converter With Resolution of VIN/2N for a Wide Range of Input and Output Voltages. 543-556 - Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray:
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. 557-567
Volume 51, Number 3, March 2016
- Michael P. Flynn:
New Associate Editor. 571 - Michael P. Flynn:
Introducing BrowZine, a Tablet and Phone-Based Reader for the JSSC. 572 - Michael P. Flynn:
Introducing Short Regular Papers. 573 - Mahdi Parvizi, Karim Allidina, Mourad N. El-Gamal:
Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 µW 0.6-4.2 GHz Current-Reuse CMOS LNA. 574-586 - Haoyu Qian, Qiyuan Liu, José Silva-Martínez, Sebastian Hoyos:
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS. 587-597 - Song Hu, Shouhei Kousai, Hua Wang:
A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique. 598-613 - Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi:
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers. 614-625 - Long Kong, Behzad Razavi:
A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer. 626-635 - Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici:
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. 636-648 - Hyungil Chae, Michael P. Flynn:
A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability. 649-659 - Rudolf Ritter, John G. Kauffman, Joachim Becker, Maurits Ortmanns:
A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection. 660-670 - Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization. 671-685 - Aatmesh Shrivastava, Divya Akella Kamakshi, Benton H. Calhoun:
A 1.5 nW, 32.768 kHz XTAL Oscillator Operational From a 0.3 V Supply. 686-696 - Inhee Lee, Dennis Sylvester, David T. Blaauw:
A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes. 697-711 - Lin Cheng, Wing-Hung Ki, Yan Lu, Tak-Sang Yim:
Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems. 712-723 - Kian Ann Ng, Yong Ping Xu:
A Low-Power, High CMRR Neural Amplifier System Employing CMOS Inverter-Based OTAs With CMFB Through Supply Rails. 724-737 - Kailiang Chen, Hae-Seung Lee, Charles G. Sodini:
A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging. 738-751 - Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov:
Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm. 752-762 - Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto:
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. 763-775 - Leonardo Vera, John R. Long:
Erratum to "A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core". 776 - K. R. Lakshmikumar:
Patent Abstracts. 777-781
Volume 51, Number 4, April 2016
- Masato Motomura, Andreia Cathelin:
Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits. 787-788 - Phillip M. Nadeau, Arun Paidimarri, Anantha P. Chandrakasan:
Ultra Low-Energy Relaxation Oscillator With 230 fJ/cycle Efficiency. 789-799 - Saleh Heidary Shalmany, Dieter Draxelmayr, Kofi A. A. Makinwa:
A ±5A Integrated Current-Sensing System With ±0.3% Gain Error and 16μA Offset From -55°C +85°C. 800-808 - Nam-Seog Kim, Jan M. Rabaey:
A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio. 809-820 - Ting-Kuei Kuan, Shen-Iuan Liu:
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques. 821-831 - Chul Kim, Siddharth Joshi, Chris M. Thomas, Sohmyung Ha, Lawrence E. Larson, Gert Cauwenberghs:
A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation. 832-844 - Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez:
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver. 845-859 - Sebastian Loeda, Jeffrey Harrison, Franck Pourchet, Andrew Adams:
A 10/20/30/40 MHz Feedforward FIR DAC Continuous-Time ΔΣ ADC With Robust Blocker Performance for Radio Receivers. 860-870 - Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon:
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. 871-880 - Namik Kocaman, Tamer A. Ali, Lakshmi P. Rao, Ullas Singh, Mohammed M. Abdul-Latif, Yang Liu, Amr Amin Hafez, Henry Park, Anand Vasani, Zhi Huang, Arvindh Iyer, Bo Zhang, Afshin Momtaz:
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. 881-892 - Chen Sun, Mark T. Wade, Michael Georgas, Sen Lin, Luca Alloatti, Benjamin Moss, Rajesh Kumar, Amir H. Atabaki, Fabio Pavanello, Jeffrey Shainline, Jason Orcutt, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic:
A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning. 893-907 - Sharvil Patil, Alin Ratiu, Dominique Morche, Yannis P. Tsividis:
A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC. 908-918 - Suyoung Bang, Jae-sun Seo, Leland Chang, David T. Blaauw, Dennis Sylvester:
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering. 919-929 - Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. 930-942 - Dina El-Damak, Anantha P. Chandrakasan:
A 10 nW-1µW Power Management IC With Integrated Battery Management and Self-Startup for Energy Harvesting Applications. 943-954 - Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Vivek Nagaraj, Theoden I. Netoff, Michael P. Flynn, Euisik Yoon:
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression. 955-965 - Jun-Suk Bang, Hyunsik Kim, Kiduk Kim, Ohjo Kwon, Choongsun Shin, Joohyung Lee, Gyu-Hyeong Cho:
A Hybrid AMOLED Driver IC for Real-Time TFT Nonuniformity Compensation. 966-978 - Josue Sanz-Robinson, Liechao Huang, Tiffany Moy, Warren Rieutort-Louis, Yingzhe Hu, Sigurd Wagner, James C. Sturm, Naveen Verma:
Large-Area Microphone Array for Audio Source Separation Based on a Hybrid Architecture Exploiting Thin-Film Electronics and CMOS. 979-991 - Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. 992-1002 - Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. 1003-1008 - Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David T. Blaauw:
A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory. 1009-1021 - Kaiyuan Yang, David T. Blaauw, Dennis Sylvester:
An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations. 1022-1031 - Kyeongryeol Bong, Injoon Hong, Gyeonghoon Kim, Hoi-Jun Yoo:
A 0.5° Error 10 mW CMOS Image Sensor-Based Gaze Estimation Processor. 1032-1040 - Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi:
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. 1041-1050 - Yukihiro Sasagawa, Atsuhiro Mori:
High-level Video Analytics PC Subsystem Using SoC With Heterogeneous Multicore Architecture. 1051-1059
Volume 51, Number 5, May 2016
- Michael P. Flynn, Pietro Andreani, SeongHwan Cho:
New Associate Editors. 1063 - Salvatore Levantino:
Introduction to the Special Section on the 2015 Radio Frequency Integrated Circuits Symposium. 1064-1065 - Mohyee Mikhemar, Masoud Kahrizi, John C. Leete, Bernd Prégardier, Nooshin Vakilian, Amir Hadji-Abdolhamid, Morteza Vadipour, Peihua Ye, Janice Chiu, Behzad Saeidi, Gerasimos Theodoratos, Med Nariman, Yuyu Chang, Behnam Mohammadi, Farzad Etemadi, Behzad Nourani, Alireza Tarighat, Paul Mudge, Zhimin Zhou, Ning Liu, Claire Guan, Kevin Juan, Rahul Magoon, Maryam Rofougaran, Ahmadreza Rofougaran:
A Rel-12 2G/3G/LTE-Advanced 3CC Cellular Receiver. 1066-1079 - Behnam Mohammadi, Masoud Kahrizi, Ahmad Mirzaei, Sining Zhou, Amir Hadji-Abdolhamid, John C. Leete, Bernd Prégardier, Med Nariman, Behzad Saeidi, Yuyu Chang, Dmitriy Rozenblit, Mohyee Mikhemar, Alireza Tarighat Mehrabani, Rahul Magoon, Maryam Rofougaran, Ahmadreza Rofougaran:
A Rel-12 2G/3G/LTE-Advanced 2CC Transmitter. 1080-1095 - Siddharth Seth, Dae Hyun Kwon, Sriramkumar Venugopalan, Sang Won Son, Yongrong Zuo, Venumadhav Bhagavatula, Jaehyun Lim, Dongjin Oh, Thomas Byunghak Cho:
A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS. 1096-1108 - Jamin J. McCue, Brian Dupaix, Lucas Duncan, Brandon Mathieu, Samantha McDonnell, Vipul J. Patel, Tony Quach, Waleed Khalil:
A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis. 1109-1124 - Tolga Dinc, Anandaroop Chakrabarti, Harish Krishnaswamy:
A 60 GHz CMOS Full-Duplex Transceiver and Link with Polarization-Based Antenna and RF Cancellation. 1125-1140 - Alaa Medra, Davide Guermandi, Kristof Vaesen, Steven Brebels, André Bourdoux, Wim Van Thillo, Piet Wambacq, Vito Giannini:
An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars. 1141-1153 - Yang Xu, Peter R. Kinget:
A Switched-Capacitor RF Front End With Embedded Programmable High-Order Filtering. 1154-1167 - Jaehun Jeong, Nicholas Collins, Michael P. Flynn:
A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators. 1168-1176 - Jaegan Ko, Ranjit Gharpurey:
A Pulsed UWB Transceiver in 65 nm CMOS With Four-Element Beamforming for 1 Gbps Meter-Range WPAN Applications. 1177-1187 - Kunhee Cho, Ranjit Gharpurey:
A Digitally Intensive Transmitter/PA Using RF-PWM With Carrier Switching in 130 nm CMOS. 1188-1199 - Wen Yuan, Vladimir Aparin, Jeremy Dunworth, Lee Seward, Jeffrey S. Walling:
A Quadrature Switched Capacitor Power Amplifier. 1200-1209 - Amir Hossein Masnadi Shirazi, Amir Nikpaik, Reza Molavi, Sam Lightbody, Hormoz Djahanshahi, Mazhareddin Taghivand, Shahriar Mirabbasi, Sudip Shekhar:
On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise. 1210-1222