default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Architecture and Code Optimization, Volume 13
Volume 13, Number 1, April 2016
- Konstantinos Koukos
, Alberto Ros, Erik Hagersten, Stefanos Kaxiras:
Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. 1:1-1:22 - Zhigang Wang, Xiaolin Wang, Fang Hou, Yingwei Luo, Zhenlin Wang:
Dynamic Memory Balancing for Virtualization. 2:1-2:25 - Xueyang Wang, Sek Meng Chai, Michael A. Isnardi, Sehoon Lim, Ramesh Karri:
Hardware Performance Counter-Based Malware Identification and Detection with Adaptive Compressive Sensing. 3:1-3:23 - Shoaib Akram, Jennifer B. Sartor, Kenzo Van Craeynest, Wim Heirman, Lieven Eeckhout:
Boosting the Priority of Garbage: Scheduling Collection on Heterogeneous Multicore Processors. 4:1-4:25 - Buse Yilmaz, Baris Aktemur, María Jesús Garzarán, Samuel N. Kamin, Furkan Kiraç:
Autotuning Runtime Specialization for Sparse Matrix-Vector Multiplication. 5:1-5:26 - Mingzhou Zhou, Bo Wu, Xipeng Shen, Yaoqing Gao, Graham Yiu:
Examining and Reducing the Influence of Sampling Errors on Feedback-Driven Optimizations. 6:1-6:24 - Amanieu D'Antras, Cosmin Gorgovan, Jim D. Garside, Mikel Luján:
Optimizing Indirect Branches in Dynamic Binary Translators. 7:1-7:25 - Luiz G. A. Martins, Ricardo Nobre, João M. P. Cardoso, Alexandre C. B. Delbem, Eduardo Marques:
Clustering-Based Selection for the Exploration of Compiler Optimization Sequences. 8:1-8:28 - Sang Wook Stephen Do, Michel Dubois:
Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions. 9:1-9:25 - Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh:
Understanding and Mitigating Covert Channels Through Branch Predictors. 10:1-10:23 - Hao Zhou, Jingling Xue:
A Compiler Approach for Exploiting Partial SIMD Parallelism. 11:1-11:26 - Gert-Jan van den Braak, Henk Corporaal:
R-GPU: A Reconfigurable GPU Architecture. 12:1-12:24 - Peng Liu, Jiyang Yu, Michael C. Huang:
Thread-Aware Adaptive Prefetcher on Multicore Systems: Improving the Performance for Multithreaded Workloads. 13:1-13:25 - Cosmin Gorgovan, Amanieu D'Antras, Mikel Luján:
MAMBO: A Low-Overhead Dynamic Binary Modification Tool for ARM. 14:1-14:26
Volume 13, Number 2, June 2016
- Panagiotis Theocharis, Bjorn De Sutter:
A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays. 15:1-15:26 - Ahmad Anbar, Olivier Serres, Engin Kayraklioglu, Abdel-Hameed A. Badawy, Tarek A. El-Ghazawi:
Exploiting Hierarchical Locality in Deep Parallel Architectures. 16:1-16:25 - Cecilia González-Alvarez, Jennifer B. Sartor, Carlos Álvarez, Daniel Jiménez-González, Lieven Eeckhout:
MInGLE: An Efficient Framework for Domain Acceleration Using Low-Power Specialized Functional Units. 17:1-17:26 - Christian Andreetta, Vivien Bégot, Jost Berthold, Martin Elsman, Fritz Henglein, Troels Henriksen, Maj-Britt Nordfang, Cosmin E. Oancea:
FinPar: A Parallel Financial Benchmark. 18:1-18:27 - Mickaël Dardaillon, Kevin Marquet, Tanguy Risset, Jérôme Martin, Henri-Pierre Charles:
A New Compilation Flow for Software-Defined Radio Applications on Heterogeneous MPSoCs. 19:1-19:25 - Jianwei Liao, François Trahay, Guoqiang Xiao:
Dynamic Process Migration Based on Block Access Patterns Occurring in Storage Servers. 20:1-20:20 - Amir Hossein Ashouri, Giovanni Mariani, Gianluca Palermo, Eunjung Park, John Cavazos, Cristina Silvano:
COBAYN: Compiler Autotuning Framework Using Bayesian Networks. 21:1-21:25 - Kypros Chrysanthou, Panayiotis Englezakis, Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides, Giorgos Dimitrakopoulos:
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. 22:1-22:26
Volume 13, Number 3, September 2016
- Sanyam Mehta, Pen-Chung Yew:
Variable Liberalization. 23:1-23:25 - Hsing Min Chen, Carole-Jean Wu, Trevor N. Mudge, Chaitali Chakrabarti:
RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory. 24:1-24:24 - Wenjie Chen, Zhibin Wang, Qin Wu, Jiuzhen Liang, Zhilei Chai:
Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C. 25:1-25:25 - Nilay Vaish, Michael C. Ferris, David A. Wood:
Optimization Models for Three On-Chip Network Problems. 26:1-26:27 - Somayeh Sardashti, André Seznec, David A. Wood:
Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache. 27:1-27:25 - Eduardo H. M. Cruz, Matthias Diener, Laércio Lima Pilla, Philippe O. A. Navaux:
Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures. 28:1-28:28 - Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Maximizing Heterogeneous Processor Performance Under Power Constraints. 29:1-29:23 - Bagus Wibowo, Abhinav Agrawal, Thomas Stanton, James Tuck:
An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation. 30:1-30:27 - List of Distinguished Reviewers ACM TACO 2014. 31:1-31:3
Volume 13, Number 4, December 2016
- Keval Vora, Rajiv Gupta, Guoqing Xu:
Synergistic Analysis of Evolving Graphs. 32:1-32:27 - Yunquan Zhang, Shigang Li, Shengen Yan, Huiyang Zhou:
A Cross-Platform SpMV Framework on Many-Core Architectures. 33:1-33:25 - Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy. 34:1-34:24 - Amir Kavyan Ziabari, Yifan Sun, Yenai Ma, Dana Schaa, José L. Abellán, Rafael Ubal, John Kim, Ajay Joshi, David R. Kaeli:
UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs. 35:1-35:25 - Tom Spink, Harry Wagstaff, Björn Franke:
Hardware-Accelerated Cross-Architecture Full-System Virtualization. 36:1-36:25 - Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan:
LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies. 37:1-37:28 - Fernando Fernandes, Lucas Weigel, Cláudio R. Jung, Philippe O. A. Navaux, Luigi Carro, Paolo Rech:
Evaluation of Histogram of Oriented Gradients Soft Errors Criticality for Automotive Applications. 38:1-38:25 - Saumay Dublish, Vijay Nagarajan, Nigel P. Topham:
Cooperative Caching for GPUs. 39:1-39:25 - Nikolaos Tampouratzis, Pavlos M. Mattheakis, Ioannis Papaefstathiou:
Accelerating Intercommunication in Highly Parallel Systems. 40:1-40:25 - Hyukwoo Park, Myungsu Cha, Soo-Mook Moon:
Concurrent JavaScript Parsing for Faster Loading of Web Apps. 41:1-41:24 - Dongliang Xiong, Kai Huang, Xiaowen Jiang, Xiaolang Yan:
Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems. 42:1-42:26 - Daniele De Sensi, Massimo Torquati, Marco Danelutto:
A Reconfiguration Algorithm for Power-Aware Parallel Applications. 43:1-43:25 - Michael R. Jantz, Forrest J. Robinson, Prasad A. Kulkarni:
Impact of Intrinsic Profiling Limitations on Effectiveness of Adaptive Optimizations. 44:1-44:26 - Marvin Damschen, Lars Bauer, Jörg Henkel:
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors. 45:1-45:24 - Zheng Li, Fang Wang, Dan Feng, Yu Hua, Jingning Liu, Wei Tong:
MaxPB: Accelerating PCM Write by Maximizing the Power Budget Utilization. 46:1-46:26 - Saurav Muralidharan, Michael Garland, Albert Sidelnik, Mary W. Hall:
Designing a Tunable Nested Data-Parallel Programming System. 47:1-47:24 - Ismail Akturk, Riad Akram, Mohammad Majharul Islam, Abdullah Muzahid, Ulya R. Karpuzcu:
Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance. 48:1-48:24 - Erik Tomusk, Christophe Dubach, Michael F. P. O'Boyle:
Selecting Heterogeneous Cores for Diversity. 49:1-49:25 - Pierre Michaud:
Some Mathematical Facts About Optimal Cache Replacement. 50:1-50:19 - Wenlei Bao, Changwan Hong, Sudheer Chunduri, Sriram Krishnamoorthy, Louis-Noël Pouchet, Fabrice Rastello, P. Sadayappan:
Static and Dynamic Frequency Scaling on Multicore CPUs. 51:1-51:26 - Tiago M. Vale, João A. Silva, Ricardo J. Dias, João M. Lourenço:
Pot: Deterministic Transactional Execution. 52:1-52:24 - Zhonghai Lu, Yuan Yao:
Aggregate Flow-Based Performance Fairness in CMPs. 53:1-53:27 - Yigit Demir, Nikos Hardavellas:
Energy-Proportional Photonic Interconnects. 54:1-54:26 - Mehmet Can Kurt, Sriram Krishnamoorthy, Gagan Agrawal, Bin Ren:
User-Assisted Store Recycling for Dynamic Task Graph Schedulers. 55:1-55:24 - Jawad Haj-Yihia, Ahmad Yasin, Yosi Ben-Asher, Avi Mendelson:
Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems. 56:1-56:25 - Alberto Scolari, Davide Basilio Bartolini, Marco Domenico Santambrogio:
A Software Cache Partitioning System for Hash-Based Caches. 57:1-57:24
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-03-08 22:01 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
