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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25
Volume 25, Number 1, January 2006
- Görschwin Fey, Rolf Drechsler:
Minimizing the number of paths in BDDs: Theory and algorithm. 4-11 - Wenjian Yu, Mengsheng Zhang, Zeyi Wang:
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. 12-18 - Kyosun Kim, Ramesh Karri, Miodrag Potkonjak:
Micropreemption synthesis: an enabling mechanism for multitask VLSI systems. 19-30 - María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Bitwise scheduling to balance the computational cost of behavioral specifications. 31-46 - Jaewon Seo, Taewhan Kim, Joonwon Lee:
Optimal intratask dynamic voltage-scaling technique and its practical extensions. 47-57 - Arijit Raychowdhury, Kaushik Roy:
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. 58-65 - Jaijeet S. Roychowdhury, Robert C. Melville:
Delivering global DC convergence for large mixed-signal circuits via homotopy/continuation methods. 66-78 - Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee:
Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications. 79-91 - Li Shang, Li-Shiuan Peh, Niraj K. Jha:
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. 92-110 - Ying Zhang, Krishnendu Chakrabarty:
A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems. 111-125 - Imad A. Ferzli, Farid N. Najm:
Analysis and verification of power grids considering process-induced leakage-current variations. 126-143 - Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda:
Optimal placement of power-supply pads and pins. 144-154 - Quming Zhou, Kartik Mohanram:
Gate sizing to radiation harden combinational logic. 155-166 - Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov:
Fast detection of data retention faults and other SRAM cell open defects. 167-180 - Qiang Xu, Nicola Nicolici:
Multifrequency TAM design for hierarchical SOCs. 181-196 - Shih-Yu Yang, Christos A. Papachristou:
A method for detecting interconnect DSM defects in systems on chip. 197-204
Volume 25, Number 2, February 2006
- Fei Su, Krishnendu Chakrabarty, Richard B. Fair:
Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges. 211-223 - Jun Zeng:
Modeling and Simulation of Electrified Droplets and Its Application to Computer-Aided Design of Digital Microfluidics. 224-233 - Jan Lienemann, Andreas Greiner, Jan G. Korvink:
Modeling, Simulation, and Optimization of Electrowetting. 234-247 - Xin Wang, Joe Kanapka, Wenjing Ye, Narayan R. Aluru, Jacob White:
Algorithms in FastStokes and Its Application to Micromachined Device Simulation. 248-257 - Yi Wang, Qiao Lin, Tamal Mukherjee:
Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic Lab-on-a-Chip Systems. 258-273 - Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White:
FFTSVD: A Fast Multiscale Boundary-Element Method Solver Suitable for Bio-MEMS and Biomolecule Simulation. 274-284 - Dmitry Vasilyev, Michal Rewienski, Jacob K. White:
Macromodel Generation for BioMEMS Components Using a Stabilized Balanced Truncation Plus Trajectory Piecewise-Linear Approach. 285-293 - Anand S. Bedekar, Yi Wang, S. Krishnamoorthy, Sachin S. Siddhaye, Shankar Sundaram:
System-Level Simulation of Flow-Induced Dispersion in Lab-on-a-Chip Systems. 294-304 - Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky:
Computer-Aided Optimization of DNA Array Design and Manufacturing. 305-320 - Anton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan:
Synthesis of Multiplexed Biofluidic Microchips. 321-333 - Karl-Friedrich Böhringer:
Modeling and Controlling Parallel Tasks in Droplet-Based Microfluidic Systems. 334-344 - Eric J. Griffith, Srinivas Akella, Mark K. Goldberg:
Performance Characterization of a Reconfigurable Planar-Array Digital Microfluidic System. 345-357 - Sungroh Yoon, Luca Benini, Giovanni De Micheli:
A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis. 358-377 - Ryan Magargle, James F. Hoburg, Tamal Mukherjee:
Microfluidic Injector Models Based on Artificial Neural Networks. 378-385
Volume 25, Number 3, March 2006
- Sangyun Kim, Peter A. Beerel:
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm. 389-402 - Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda:
Verification of timed circuits with failure-directed abstractions. 403-412 - Kaijie Wu, Ramesh Karri:
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. 413-422 - Jason Helge Anderson, Farid N. Najm:
Active leakage power optimization for FPGAs. 423-437 - Dongkun Shin, Jihong Kim:
Dynamic voltage scaling of mixed task sets in priority-driven systems. 438-453 - Hongmei Li, Cole E. Zemke, Giorgos Manetas, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris:
An automated and efficient substrate noise analysis tool. 454-468 - Ruibing Lu, Cheng-Kok Koh:
Performance analysis of latency-insensitive systems. 469-483 - Zhuo Li, Weiping Shi:
An O(bn2) time algorithm for optimal buffer insertion with b buffer types. 484-489 - Muhammet Mustafa Ozdal, Martin D. F. Wong:
Algorithmic study of single-layer bus routing for high-speed boards. 490-503 - Navaratnasothie Selvakkumaran, George Karypis:
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization. 504-517 - Akshay Sharma, Carl Ebeling, Scott Hauck:
PipeRoute: a pipelining-aware router for reconfigurable architectures. 518-532 - Andrew B. Kahng, Sherief Reda:
New and improved BIST diagnosis methods from combinatorial Group testing theory. 533-543 - Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. 544-557 - Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Analysis and methodology for multiple-fault diagnosis. 558-575 - Joonhwan Yi, John P. Hayes:
High-level delay test generation for modular circuits. 576-590 - Irith Pomeranz, Sudhakar M. Reddy:
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. 591-596 - Hua Tang, Alex Doboli:
High-level synthesis of ΔΣ Modulator topologies optimized for complexity, sensitivity, and power consumption. 597-607
Volume 25, Number 4, April 2006
- Qinghua Liu, Malgorzata Marek-Sadowska:
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. 611-624 - Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar:
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. 625-636 - Tung-Chieh Chen, Yao-Wen Chang:
Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. 637-650 - Baris Taskin, Ivan S. Kourtev:
Delay Insertion Method in Clock Skew Scheduling. 651-663 - Jaskirat Singh, Sachin S. Sapatnekar:
Partition-Based Algorithm for Power Grid Design Using Locality. 664-677 - Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm. 678-691 - Brent Goplen, Sachin S. Sapatnekar:
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. 692-709 - James D. Ma, Rob A. Rutenbar:
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. 710-724 - Yukiko Kubo, Atsushi Takahashi:
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. 725-733 - Di Wu, Jiang Hu, Rabi N. Mahapatra:
Antenna Avoidance in Layer Assignment. 734-738
Volume 25, Number 5, May 2006
- Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. 743-755 - Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein:
Hardware compilation of application-specific memory-access interconnect. 756-771 - Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh:
Optimal register sharing for high-level synthesis of SSA form programs. 772-779 - Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain:
On partitioning and symbolic model checking. 780-788 - Tsutomu Sasao:
Analysis and synthesis of weighted-sum functions. 789-796 - Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias:
Comparison of two designs for the multifunction vehicle bus. 797-805 - Ying Yi, Roger F. Woods:
Hierarchical synthesis of complex DSP functions using IRIS. 806-820 - Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses. 821-836 - Srinivas Bodapati, Farid N. Najm:
High-level current macro model for logic blocks. 837-855 - Yan Feng, Dinesh P. Mehta:
Module relocation to obtain feasible constrained floorplans. 856-866 - Premachandran R. Menon, Weifeng Xu, Russell Tessier:
Design-specific path delay testing in lookup-table-based FPGAs. 867-877 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Concurrent detection of erroneous responses in linear analog circuits. 878-891 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Modeling and analysis of crosstalk noise in coupled RLC interconnects. 892-901 - Rüdiger Ebendt, Rolf Drechsler:
Effect of improved lower bounds in dynamic BDD reordering. 902-909 - Kooho Jung, William R. Eisenstadt, Robert M. Fox:
SPICE-based mixed-mode S-parameter calculations for four-port and three-port circuits. 909-913 - Hong-Sik Kim, Sungho Kang:
Increasing encoding efficiency of LFSR reseeding-based test compression. 913-917 - Xun Liu, Yuantao Peng, Marios C. Papaefthymiou:
Practical repeater insertion for low power: what repeater library do we need? 917-924 - Ewout Martens, Georges G. E. Gielen:
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models. 924-932 - Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. 932-938
Volume 25, Number 6, June 2006
- Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Chuanjin Richard Shi:
Multilevel symmetry-constraint generation for retargeting large analog layouts. 945-960 - Shih-Hsu Huang, Yow-Tyng Nieh:
Synthesis of nonzero clock skew circuits. 961-976 - Alan Mishchenko, Robert K. Brayton:
A theory of nondeterministic networks. 977-999 - Vivek V. Shende, Stephen S. Bullock, Igor L. Markov:
Synthesis of quantum-logic circuits. 1000-1010 - Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Linear cofactor relationships in Boolean functions. 1011-1023 - Ravindra Jejurikar, Rajesh K. Gupta:
Energy-aware task scheduling with task synchronization for embedded real-time systems. 1024-1037 - Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda:
Impact of stress-induced backflow on full-chip electromigration risk assessment. 1038-1046 - Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum:
Compact modeling of on-chip ESD protection devices using Verilog-A. 1047-1063 - Debjit Sinha, Hai Zhou:
Gate-size optimization under timing constraints for coupling-noise reduction. 1064-1074 - Peter G. Sassone, Sung Kyu Lim:
Traffic: a novel geometric algorithm for fast wire-optimized floorplanning. 1075-1086 - Zhao Li, Chuanjin Richard Shi:
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. 1087-1103 - Tao Jiang, R. D. (Shawn) Blanton:
Inductive fault analysis of surface-micromachined MEMS. 1104-1116 - Manan Syal, Michael S. Hsiao:
New techniques for untestable fault identification in sequential circuits. 1117-1131 - Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
Three-dimensional place and route for FPGAs. 1132-1140 - Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. 1140-1145 - Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. 1146-1154 - Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis:
A high-performance data path for synthesizing DSP kernels. 1154-1162 - Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri:
Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. 1163-1169 - Irith Pomeranz, Sudhakar M. Reddy:
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. 1170-1175 - Anand Rajaram, Jiang Hu, Rabi N. Mahapatra:
Reducing clock skew variability via crosslinks. 1176-1182 - Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen:
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. 1183-1191
Volume 25, Number 7, July 2006
- Kris Tiri, Ingrid Verbauwhede:
A digital design flow for secure integrated circuits. 1197-1208 - Laura Pozzi, Kubilay Atasu, Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets. 1209-1229 - Christopher Umans, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
Complexity of two-level logic minimization. 1230-1246 - Jongsun Park, Khurram Muhammad, Kaushik Roy:
Efficient modeling of 1/falpha/ noise using multirate process. 1247-1256 - Guoyong Shi, Bo Hu, Chuanjin Richard Shi:
On symbolic model order reduction. 1257-1272 - Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical interconnect metrics for physical-design optimization. 1273-1288 - Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim:
Profile-guided microarchitectural floor planning for deep submicron processor design. 1289-1300 - Andrew B. Kahng, Sherief Reda:
Wirelength minimization for min-cut placements via placement feedback. 1301-1312 - Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov:
Min-cut floorplacement. 1313-1326 - Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak:
A statistical methodology for wire-length prediction. 1327-1336 - Peng Rong, Massoud Pedram:
Battery-aware power management based on Markovian decision processes. 1337-1349 - Munkang Choi, Linda S. Milor:
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. 1350-1367 - Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury:
An integrated DFT solution for mixed-signal SOCs. 1368-1377 - Luc Knockaert, Tom Dhaene:
Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models. 1377-1381 - Knockaert Radecka, Zeljko Zilic:
Arithmetic transforms for compositions of sequential and imprecise datapaths. 1382-1391 - Chuanjin Richard Shi, Michael W. Tian, Guoyong Shi:
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. 1392-1400 - Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen:
Analytical model for crosstalk and intersymbol interference in point-to-point buses. 1400-1410 - Dan Zhao, Shambhu J. Upadhyaya, Martin Margala:
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip. 1411-1418
Volume 25, Number 8, August 2006
- Hua Tang, Hui Zhang, Alex Doboli:
Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling. 1421-1440 - Behzad Akbarpour, Sofiène Tahar:
An approach for the formal verification of DSP designs using Theorem proving. 1441-1457 - Hiren D. Patel, Deepak Mathaikutty, David Berner, Sandeep K. Shukla:
CARH: service-oriented architecture for validating system-level designs. 1458-1474 - Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Gate-length biasing for runtime-leakage control. 1475-1485 - Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. 1486-1495 - Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He:
Wideband passive multiport model order reduction and realization of RLCM circuits. 1496-1509 - Muhammet Mustafa Ozdal, Martin D. F. Wong:
Algorithms for simultaneous escape routing and Layer assignment of dense PCBs. 1510-1522 - PariVallal Kannan, Dinesh Bhatia:
Interconnect estimation for FPGAs. 1523-1534 - Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
Pseudofunctional testing. 1535-1546 - Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris