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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 21
Volume 21, Number 1, January 2013
- Dong Hyuk Woo, Nak Hee Seong, Hsien-Hsin S. Lee:
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV. 1-13
- Liang Li, Robert G. Maunder
, Bashir M. Al-Hashimi, Lajos Hanzo:
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks. 14-22 - Mario Garrido, Jesús Grajal, Miguel A. Sánchez Marcos, Oscar Gustafsson:
Pipelined Radix-2k Feedforward FFT Architectures. 23-32 - Jui-Hung Hsieh, Tian-Sheuan Chang:
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications. 33-42 - Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou:
STBC-OFDM Downlink Baseband Receiver for Mobile WMAN. 43-54 - Davide De Caro:
Glitch-Free NAND-Based Digitally Controlled Delay-Lines. 55-66 - Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang:
A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique. 67-77 - Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal:
Formal Verification of Architectural Power Intent. 78-91 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits. 92-101 - Jianwei Dai, Lei Wang:
An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy. 102-112 - Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch:
An Analytical Latency Model for Networks-on-Chip. 113-123 - Irith Pomeranz:
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure. 124-132 - Marius Monton, Jakob Engblom, Mark Burton:
Checkpointing for Virtual Platforms and SystemC-TLM. 133-141 - Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan:
Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate. 142-147 - Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson:
Scaling Energy Per Operation via an Asynchronous Pipeline. 147-151 - Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. 151-156 - Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan:
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes. 156-159 - Yunus Emre, Chaitali Chakrabarti:
Techniques for Compensating Memory Errors in JPEG2000. 159-163 - Kan Takeuchi, Masaki Shimada, Takao Sato, Yusaku Katsuki, Hiroumi Yoshikawa, Hiroaki Matsushita:
Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise. 164-168 - Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials. 168-173 - Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim:
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. 173-177 - Phi-Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim:
An On-Chip Network Fabric Supporting Coarse-Grained Processor Array. 178-182 - Juan Antonio Gómez Galán, Manuel Pedro, Trinidad Sanchez-Rodriguez, Fernando Muñoz, Ramón González Carvajal, Antonio J. López-Martín:
A Very Linear Low-Pass Filter with Automatic Frequency Tuning. 182-187 - Taesang Cho, Hanho Lee:
A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications. 187-191
Volume 21, Number 2, February 2013
- Davide Rossi, Claudio Mucci, Fabio Campi, Simone Spolzino, Luca Vanzolini, Henning Sahlbach, Sean Whitty, Rolf Ernst, Wolfram Putzke-Röming, Roberto Guerrieri:
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor. 193-205 - Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality. 206-216 - Pramod Kumar Meher, Sang Yoon Park:
CORDIC Designs for Fixed Angle of Rotation. 217-228 - Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King:
Application-Driven End-to-End Traffic Predictions for Low Power NoC Design. 229-238 - Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. 239-249 - I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. 250-258 - Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo:
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. 259-269 - You-Gang Chen, Hen-Wai Tsao, Chorng-Sii Hwang:
A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction. 270-280 - Jaeyong Chung, Joonsung Park, Jacob A. Abraham:
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. 281-291 - Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu:
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. 292-305 - Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. 306-319 - Joon-Sung Yang, Nur A. Touba:
Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. 320-328 - Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. 329-341 - Marshnil Vipin Dave, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects. 342-353 - Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng:
Modeling and Analysis of Power Distribution Networks in 3-D ICs. 354-366 - Kai-Chiang Wu, Diana Marculescu:
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits. 367-379 - Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark:
Low Complexity Out-of-Order Issue Logic Using Static Circuits. 380-384 - Jiafeng Xie, Jianjun He, Pramod Kumar Meher:
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. 385-389
Volume 21, Number 3, March 2013
- Yehea I. Ismail:
Editorial Appointments for the 2013-2014 Term. 393-412 - Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao:
Power-Up Sequence Control for MTCMOS Designs. 413-423 - S. Man Ho Ho, Yanqing Ai, Thomas Chun-Pong Chau, Steve C. L. Yuen, Oliver Chiu-sing Choy, Philip Heng Wai Leong, Kong-Pang Pun:
Architecture and Design Flow for a Highly Efficient Structured ASIC. 424-433 - Santosh Ghosh, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform. 434-442 - Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. 443-453 - Sehun Kook, Hyun Woo Choi, Abhijit Chatterjee:
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements. 454-464 - Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu:
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. 465-474 - Irith Pomeranz:
Computing Two-Pattern Test Cubes for Transition Path Delay Faults. 475-485 - Erin G. Fong, Nathaniel J. Guilar, Travis Kleeburg, Hai Pham, Diego R. Yankelevich, Rajeevan Amirtharajah:
Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance. 486-497 - Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. 498-511 - Josep Rius:
IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption. 512-522 - Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang:
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. 523-532 - Hailong Jiao, Volkan Kursun:
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. 533-545 - Kwan Wai Li, Ka Nang Leung, Lincoln Lai Kan Leung:
Sub-mW $LC$ Dual-Input Injection-Locked Oscillator for Autonomous WBSNs. 546-553 - Pierce Chuang, David Li, Manoj Sachdev:
Constant Delay Logic Style. 554-565 - Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny:
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. 566-570 - Emad Ebrahimi, Sasan Naseh:
A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling. 571-574 - Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim:
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor. 575-579 - Abhishek A. Sinkar, Taejoon Park, Nam Sung Kim:
Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability. 580-584 - Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. 584-588 - Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung:
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD. 589-592 - Xiwen Zhang, Hoi Lee:
Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate and Substrate Control. 593-596 - Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang:
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. 597-601
Volume 21, Number 4, April 2013
- Kanad Basu, Prabhat Mishra:
RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation. 605-613 - Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, Bin Liang:
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes. 614-623 - Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang:
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. 624-635 - Gwo-Long Li, Tzu-Yu Chen, Meng-Wei Shen, Meng-Hsun Wen, Tian-Sheuan Chang:
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder. 636-647 - Tasreen Charania, Ajoy Opal, Manoj Sachdev:
Analysis and Design of On-Chip Decoupling Capacitors. 648-658 - Yupeng Chen, Bertil Schmidt, Douglas L. Maskell:
Reconfigurable Accelerator for the Word-Matching Stage of BLASTN. 659-669 - Koushik Chakraborty, Sanghamitra Roy:
Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems. 670-679 - Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman:
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation. 680-691 - Katherine Shu-Min Li:
CusNoC: Fast Full-Chip Custom NoC Generation. 692-705 - Liang Shi, Jianhua Li, Chun Jason Xue, Xuehai Zhou:
Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems. 706-719 - Kai-Jiun Yang, Shang-Ho Tsai, Gene C. H. Chuang:
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems. 720-731 - Hesam Amir Aslanzadeh, Erik John Pankratz, Chinmaya Mishra, Edgar Sánchez-Sinencio:
Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning. 732-746 - Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, An-Yeu Wu:
Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems. 747-760 - David B. Thomas, Wayne Luk:
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. 761-770 - Yangyang Pan, Yiran Li, Hongbin Sun, Wei Xu, Nanning Zheng, Tong Zhang:
Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs. 771-775 - Irith Pomeranz:
Broadside and Skewed-Load Tests Under Primary Input Constraints. 776-780 - Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye:
Supply Noise Suppression by Triple-Well Structure. 781-785 - Giorgos Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures. 786-790 - Keshab K. Parhi:
Comments on "Low-energy CSMT carry generators and binary adders". 791
Volume 21, Number 5, May 2013
- Supriya Karmakar, John A. Chandy, Faquir C. Jain:
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs. 793-806 - Haitham Eissa, Rami Fathy Salem, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, Mohamed Dessouky, David Nairn, Mohab H. Anis:
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow. 807-820 - Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. 821-833 - Mojtaba Mahdavi, Mahdi Shabany:
Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain. 834-847 - Mahdi Shabany, Ameer Youssef, P. Glenn Gulak:
High-Throughput 0.13-µm CMOS Lattice Reduction Core Supporting 880 Mb/s Detection. 848-861 - Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim:
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. 862-874 - Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen:
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. 875-886 - Behnam Ghavami, Mohsen Raji, Hossein Pedram, Massoud Pedram:
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits. 887-900 - Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay:
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed. 901-909 - Suhaib A. Fahmy, A. R. Mohan:
Architecture for Real-Time Nonparametric Probability Density Function Estimation. 910-920 - Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo:
1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor. 921-933 - Ali Peiravi, Mohammad Asyaei:
Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates. 934-943 - Zhigang Hao, Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle:
Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks. 944-957 - Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. 958-970 - Hiroaki Inoue, Takashi Takenaka, Masato Motomura:
C-Based Complex Event Processing on Reconfigurable Hardware. 971-974 - Wei Zhang, Hao Wang, Boyang Pan:
Reduced-Complexity LCC Reed-Solomon Decoder Based on Unified Syndrome Computation. 974-978 - Asaf Kaizerman, Sagi Fisher, Alexander Fish:
Subthreshold Dual Mode Logic. 979-983 - Renatas Jakushokas, Eby G. Friedman:
Power Network Optimization Based on Link Breaking Methodology. 983-987
Volume 21, Number 6, June 2013
- Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms. 989-999 - Lucas Francisco Wanner, Charwak Apte, Rahul Balani, Puneet Gupta, Mani B. Srivastava:
Hardware Variability-Aware Duty Cycling for Embedded Sensors. 1000-1012 - Young-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn, Kangmin Lee:
MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache. 1013-1026 - Isaak Yang, Sung Hoon Jung, Kwang-Hyun Cho:
Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication. 1027-1040 - Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
Dual-Level Adaptive Supply Voltage System for Variation Resilience. 1041-1052 - Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing:
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. 1053-1066 - Marcel Gort, Jason Helge Anderson:
Combined Architecture/Algorithm Approach to Fast FPGA Routing. 1067-1079 - Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Shreepad Panth, Sung Kyu Lim, Jongman Kim:
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures. 1080-1093 - Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin Hsing-Mean Sha:
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory. 1094-1102 - Eddie Hung, Steven J. E. Wilton:
Scalable Signal Selection for Post-Silicon Debug. 1103-1115 - Ender Yilmaz, Sule Ozev, Kenneth M. Butler:
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring. 1116-1128 - Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor:
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects. 1129-1142 - Meng-Chou Chang, Wei-Hsiang Chang:
Asynchronous Fine-Grain Power-Gated Logic. 1143-1153 - Jun-Ren Su, Te-Wen Liao, Chung-Chih Hung:
All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle. 1154-1164 - Sumit Jagdish Darak, A. Prasad Vinod, Edmund Ming-Kit Lai:
Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses. 1165-1169 - Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen:
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints. 1170-1174 - Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. 1175-1179
Volume 21, Number 7, July 2013
- Yalcin Yilmaz, Pinaki Mazumder:
Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets. 1181-1188