BibTeX records: Stevo Bailey

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@article{DBLP:journals/jssc/WangBHBORWRAN19,
  author    = {Angie Wang and
               Woo{-}Rham Bae and
               Jaeduk Han and
               Stevo Bailey and
               Orhan Ocal and
               Paul Rigge and
               Zhongkai Wang and
               Kannan Ramchandran and
               Elad Alon and
               Borivoje Nikolic},
  title     = {A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral
               Analysis {RISC-V} SoC in 16-nm FinFET},
  journal   = {J. Solid-State Circuits},
  volume    = {54},
  number    = {7},
  pages     = {1993--2008},
  year      = {2019},
  url       = {https://doi.org/10.1109/JSSC.2019.2913099},
  doi       = {10.1109/JSSC.2019.2913099},
  timestamp = {Fri, 05 Jul 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/WangBHBORWRAN19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/HanCBWBWNWLNA19,
  author    = {Jaeduk Han and
               Eric Chang and
               Stevo Bailey and
               Zhongkai Wang and
               Woo{-}Rham Bae and
               Angie Wang and
               Nathan Narevsky and
               Amy Whitcombe and
               Pengpeng Lu and
               Borivoje Nikolic and
               Elad Alon},
  title     = {A Generated 7GS/s 8b Time-Interleaved {SAR} {ADC} with 38.2dB {SNDR}
               at Nyquist in 16nm {CMOS} FinFET},
  booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2019, Austin,
               TX, USA, April 14-17, 2019},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/CICC.2019.8780169},
  doi       = {10.1109/CICC.2019.8780169},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/cicc/HanCBWBWNWLNA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/BaileyHRLCMWMIW18,
  author    = {Stevo Bailey and
               Jaeduk Han and
               Paul Rigge and
               Richard Lin and
               Eric Chang and
               Howard Mao and
               Zhongkai Wang and
               Chick Markley and
               Adam M. Izraelevitz and
               Angie Wang and
               Nathan Narevsky and
               Woo{-}Rham Bae and
               Steve Shauck and
               Sergio Montano and
               Justin Norsworthy and
               Munir Razzaque and
               Wen Hau Ma and
               Akalu Lentiro and
               Matthew Doerflein and
               Darin Heckendorn and
               Jim McGrath and
               Franco DeSeta and
               Ronen Shoham and
               Mike Stellfox and
               Mark Snowden and
               Joseph Cole and
               Dan Fuhrman and
               Brian C. Richards and
               Jonathan Bachrach and
               Elad Alon and
               Borivoje Nikolic},
  title     = {A Generated Multirate Signal Analysis {RISC-V} SoC in 16nm FinFET},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
               Taiwan, November 5-7, 2018},
  pages     = {285--288},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/ASSCC.2018.8579326},
  doi       = {10.1109/ASSCC.2018.8579326},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/asscc/BaileyHRLCMWMIW18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/BaileyWMHJMWN18,
  author    = {Stevo Bailey and
               John Wright and
               Nandish Mehta and
               Rachel Hochman and
               Robert Jarnot and
               Vladimir Milovanovic and
               Dan Werthimer and
               Borivoje Nikolic},
  title     = {A 28nm {FDSOI} 8192-point digital {ASIC} spectrometer from a Chisel
               generator},
  booktitle = {2018 {IEEE} Custom Integrated Circuits Conference, {CICC} 2018, San
               Diego, CA, USA, April 8-11, 2018},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/CICC.2018.8357062},
  doi       = {10.1109/CICC.2018.8357062},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/cicc/BaileyWMHJMWN18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/WangBHBROWRAN18,
  author    = {Angie Wang and
               Woo{-}Rham Bae and
               Jaeduk Han and
               Stevo Bailey and
               Paul Rigge and
               Orhan Ocal and
               Zhongkai Wang and
               Kannan Ramchandran and
               Elad Alon and
               Borivoje Nikolic},
  title     = {A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz
               Resolution Sparse Spectral Analysis {RISC-V} SoC in 16-nm FinFET},
  booktitle = {44th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2018,
               Dresden, Germany, September 3-6, 2018},
  pages     = {322--325},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/ESSCIRC.2018.8494317},
  doi       = {10.1109/ESSCIRC.2018.8494317},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/esscirc/WangBHBROWRAN18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KellerCZKPLBBCD17,
  author    = {Ben Keller and
               Martin Cochet and
               Brian Zimmer and
               Jaehwa Kwak and
               Alberto Puggelli and
               Yunsup Lee and
               Milovan Blagojevic and
               Stevo Bailey and
               Pi{-}Feng Chiu and
               Palmer Dabbelt and
               Colin Schmidt and
               Elad Alon and
               Krste Asanovic and
               Borivoje Nikolic},
  title     = {A {RISC-V} Processor SoC With Integrated Power Management at Submicrosecond
               Timescales in 28 nm {FD-SOI}},
  journal   = {J. Solid-State Circuits},
  volume    = {52},
  number    = {7},
  pages     = {1863--1875},
  year      = {2017},
  url       = {https://doi.org/10.1109/JSSC.2017.2690859},
  doi       = {10.1109/JSSC.2017.2690859},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/jssc/KellerCZKPLBBCD17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WangRDMBHCDAN17,
  author    = {Angie Wang and
               Brian C. Richards and
               Palmer Dabbelt and
               Howard Mao and
               Stevo Bailey and
               Jaeduk Han and
               Eric Chang and
               James Dunn and
               Elad Alon and
               Borivoje Nikolic},
  title     = {A 0.37mm\({}^{\mbox{2}}\) LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable
               2\({}^{\mbox{n}}\)3\({}^{\mbox{m}}\)5\({}^{\mbox{k}}\) {FFT} accelerator
               integrated with a {RISC-V} core in 16nm FinFET},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2017, Seoul,
               Korea (South), November 6-8, 2017},
  pages     = {305--308},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://doi.org/10.1109/ASSCC.2017.8240277},
  doi       = {10.1109/ASSCC.2017.8240277},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/asscc/WangRDMBHCDAN17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/LeeWCZKPKJBBCAR16,
  author    = {Yunsup Lee and
               Andrew Waterman and
               Henry Cook and
               Brian Zimmer and
               Ben Keller and
               Alberto Puggelli and
               Jaehwa Kwak and
               Ruzica Jevtic and
               Stevo Bailey and
               Milovan Blagojevic and
               Pi{-}Feng Chiu and
               Rimas Avizienis and
               Brian C. Richards and
               Jonathan Bachrach and
               David A. Patterson and
               Elad Alon and
               Bora Nikolic and
               Krste Asanovic},
  title     = {An Agile Approach to Building {RISC-V} Microprocessors},
  journal   = {{IEEE} Micro},
  volume    = {36},
  number    = {2},
  pages     = {8--20},
  year      = {2016},
  url       = {https://doi.org/10.1109/MM.2016.11},
  doi       = {10.1109/MM.2016.11},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/micro/LeeWCZKPKJBBCAR16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/KellerCZLBKPBCD16,
  author    = {Ben Keller and
               Martin Cochet and
               Brian Zimmer and
               Yunsup Lee and
               Milovan Blagojevic and
               Jaehwa Kwak and
               Alberto Puggelli and
               Stevo Bailey and
               Pi{-}Feng Chiu and
               Palmer Dabbelt and
               Colin Schmidt and
               Elad Alon and
               Krste Asanovic and
               Borivoje Nikolic},
  title     = {Sub-microsecond adaptive voltage scaling in a 28nm {FD-SOI} processor
               SoC},
  booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
               Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
  pages     = {269--272},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ESSCIRC.2016.7598294},
  doi       = {10.1109/ESSCIRC.2016.7598294},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/esscirc/KellerCZLBKPBCD16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JevticLBBAAN15,
  author    = {Ruzica Jevtic and
               Hanh{-}Phuc Le and
               Milovan Blagojevic and
               Stevo Bailey and
               Krste Asanovic and
               Elad Alon and
               Borivoje Nikolic},
  title     = {Per-Core {DVFS} With Switched-Capacitor Converters for Energy Efficiency
               in Manycore Processors},
  journal   = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume    = {23},
  number    = {4},
  pages     = {723--730},
  year      = {2015},
  url       = {https://doi.org/10.1109/TVLSI.2014.2316919},
  doi       = {10.1109/TVLSI.2014.2316919},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/tvlsi/JevticLBBAAN15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/LeeZWPKJKBBCCAR15,
  author    = {Yunsup Lee and
               Brian Zimmer and
               Andrew Waterman and
               Alberto Puggelli and
               Jaehwa Kwak and
               Ruzica Jevtic and
               Ben Keller and
               Stevo Bailey and
               Milovan Blagojevic and
               Pi{-}Feng Chiu and
               Henry Cook and
               Rimas Avizienis and
               Brian C. Richards and
               Elad Alon and
               Borivoje Nikolic and
               Krste Asanovic},
  title     = {Raven: {A} 28nm {RISC-V} vector processor with integrated switched-capacitor
               {DC-DC} converters and adaptive clocking},
  booktitle = {2015 {IEEE} Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August
               22-25, 2015},
  pages     = {1--45},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477469},
  doi       = {10.1109/HOTCHIPS.2015.7477469},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/hotchips/LeeZWPKJKBBCCAR15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZimmerLPKJKBBCL15,
  author    = {Brian Zimmer and
               Yunsup Lee and
               Alberto Puggelli and
               Jaehwa Kwak and
               Ruzica Jevtic and
               Ben Keller and
               Stevo Bailey and
               Milovan Blagojevic and
               Pi{-}Feng Chiu and
               Hanh{-}Phuc Le and
               Po{-}Hung Chen and
               Nicholas Sutardja and
               Rimas Avizienis and
               Andrew Waterman and
               Brian C. Richards and
               Philippe Flatresse and
               Elad Alon and
               Krste Asanovic and
               Borivoje Nikolic},
  title     = {A {RISC-V} vector processor with tightly-integrated switched-capacitor
               {DC-DC} converters in 28nm {FDSOI}},
  booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2015, Kyoto, Japan, June 17-19,
               2015},
  pages     = {316},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://doi.org/10.1109/VLSIC.2015.7231305},
  doi       = {10.1109/VLSIC.2015.7231305},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/vlsic/ZimmerLPKJKBBCL15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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