BibTeX records: Emmanuel Casseau

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@inproceedings{DBLP:conf/dasip/DobiasCS18,
  author    = {Petr Dobi{\'{a}}s and
               Emmanuel Casseau and
               Oliver Sinnen},
  title     = {Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant
               Scheduling on Embedded Multiprocessor Systems},
  booktitle = {2018 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2018, Porto, Portugal, October 10-12, 2018},
  pages     = {100--105},
  year      = {2018},
  crossref  = {DBLP:conf/dasip/2018},
  url       = {https://doi.org/10.1109/DASIP.2018.8597044},
  doi       = {10.1109/DASIP.2018.8597044},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/DobiasCS18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/scopes/DobiasCS18,
  author    = {Petr Dobi{\'{a}}s and
               Emmanuel Casseau and
               Oliver Sinnen},
  title     = {Restricted Scheduling Windows for Dynamic Fault-Tolerant Primary/Backup
               Approach-Based Scheduling on Embedded Systems},
  booktitle = {Proceedings of the 21st International Workshop on Software and Compilers
               for Embedded Systems, {SCOPES} 2018, Sankt Goar, Germany, May 28-30,
               2018},
  pages     = {27--30},
  year      = {2018},
  crossref  = {DBLP:conf/scopes/2018},
  url       = {https://doi.org/10.1145/3207719.3207724},
  doi       = {10.1145/3207719.3207724},
  timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/scopes/DobiasCS18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/XiaoWLC17,
  author    = {Chenglong Xiao and
               Shanshan Wang and
               Wanjun Liu and
               Emmanuel Casseau},
  title     = {Parallel custom instruction identification for extensible processors},
  journal   = {Journal of Systems Architecture - Embedded Systems Design},
  volume    = {76},
  pages     = {149--159},
  year      = {2017},
  url       = {https://doi.org/10.1016/j.sysarc.2016.11.011},
  doi       = {10.1016/j.sysarc.2016.11.011},
  timestamp = {Thu, 28 Dec 2017 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/jsa/XiaoWLC17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/WaliCT17,
  author    = {Imran Wali and
               Emmanuel Casseau and
               Arnaud Tisserand},
  title     = {An efficient framework for design and assessment of arithmetic operators
               with Reduced-Precision Redundancy},
  booktitle = {2017 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2017, Dresden, Germany, September 27-29, 2017},
  pages     = {1--6},
  year      = {2017},
  crossref  = {DBLP:conf/dasip/2017},
  url       = {https://doi.org/10.1109/DASIP.2017.8122117},
  doi       = {10.1109/DASIP.2017.8122117},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/WaliCT17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/WangXLC16,
  author    = {Shanshan Wang and
               Chenglong Xiao and
               Wanjun Liu and
               Emmanuel Casseau},
  title     = {A comparison of heuristic algorithms for custom instruction selection},
  journal   = {Microprocessors and Microsystems - Embedded Hardware Design},
  volume    = {45},
  pages     = {176--186},
  year      = {2016},
  url       = {https://doi.org/10.1016/j.micpro.2016.05.001},
  doi       = {10.1016/j.micpro.2016.05.001},
  timestamp = {Thu, 28 Dec 2017 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/mam/WangXLC16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/crowncom/TranGC16,
  author    = {Mai{-}Thanh Tran and
               Matthieu Gautier and
               Emmanuel Casseau},
  title     = {On the FPGA-Based Implementation of a Flexible Waveform from a High-Level
               Description: Application to {LTE} {FFT} Case Study},
  booktitle = {Cognitive Radio Oriented Wireless Networks - 11th International Conference,
               {CROWNCOM} 2016, Grenoble, France, May 30 - June 1, 2016, Proceedings},
  pages     = {545--557},
  year      = {2016},
  crossref  = {DBLP:conf/crowncom/2016},
  url       = {https://doi.org/10.1007/978-3-319-40352-6\_45},
  doi       = {10.1007/978-3-319-40352-6\_45},
  timestamp = {Fri, 19 May 2017 01:25:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/crowncom/TranGC16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/TranCG16,
  author    = {Mai{-}Thanh Tran and
               Emmanuel Casseau and
               Matthieu Gautier},
  title     = {Demo abstract: FPGA-based implementation of a flexible {FFT} dedicated
               to {LTE} standard},
  booktitle = {2016 Conference on Design and Architectures for Signal and Image Processing
               (DASIP), Rennes, France, October 12-14, 2016},
  pages     = {241--242},
  year      = {2016},
  crossref  = {DBLP:conf/dasip/2016},
  url       = {https://doi.org/10.1109/DASIP.2016.7853833},
  doi       = {10.1109/DASIP.2016.7853833},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/TranCG16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/YviquelSJTRC15,
  author    = {Herv{\'{e}} Yviquel and
               Alexandre Sanchez and
               Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
               Jarmo Takala and
               Micka{\"{e}}l Raulet and
               Emmanuel Casseau},
  title     = {Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs},
  journal   = {Signal Processing Systems},
  volume    = {80},
  number    = {1},
  pages     = {121--136},
  year      = {2015},
  url       = {https://doi.org/10.1007/s11265-014-0953-5},
  doi       = {10.1007/s11265-014-0953-5},
  timestamp = {Mon, 06 Nov 2017 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/vlsisp/YviquelSJTRC15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/MartinEDNCO15,
  author    = {Kevin J. M. Martin and
               Yvan Eustache and
               Jean{-}Philippe Diguet and
               Thanh Dinh Ngo and
               Emmanuel Casseau and
               Yaset Oliva},
  title     = {Compa backend: {A} dynamic runtime for the execution of dataflow programs
               onto multi-core platforms},
  booktitle = {2015 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2015, Krakow, Poland, September 23-25, 2015},
  pages     = {1--2},
  year      = {2015},
  crossref  = {DBLP:conf/dasip/2015},
  url       = {https://doi.org/10.1109/DASIP.2015.7367246},
  doi       = {10.1109/DASIP.2015.7367246},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/MartinEDNCO15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/WangXLCY15,
  author    = {Shanshan Wang and
               Chenglong Xiao and
               Wanjun Liu and
               Emmanuel Casseau and
               Xiao Yang},
  title     = {Selecting most profitable instruction-set extensions using ant colony
               heuristic},
  booktitle = {2015 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2015, Krakow, Poland, September 23-25, 2015},
  pages     = {1--7},
  year      = {2015},
  crossref  = {DBLP:conf/dasip/2015},
  url       = {https://doi.org/10.1109/DASIP.2015.7367250},
  doi       = {10.1109/DASIP.2015.7367250},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/WangXLCY15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MetairieTC15,
  author    = {J{\'{e}}r{\'{e}}my M{\'{e}}tairie and
               Arnaud Tisserand and
               Emmanuel Casseau},
  title     = {Small {FPGA} Based Multiplication-Inversion Unit for Normal Basis
               Representation in GF(2m)},
  booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
               Montpellier, France, July 8-10, 2015},
  pages     = {440--445},
  year      = {2015},
  crossref  = {DBLP:conf/isvlsi/2015},
  url       = {https://doi.org/10.1109/ISVLSI.2015.32},
  doi       = {10.1109/ISVLSI.2015.32},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/MetairieTC15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/XiaoCWL14,
  author    = {Chenglong Xiao and
               Emmanuel Casseau and
               Shanshan Wang and
               Wanjun Liu},
  title     = {Automatic custom instruction identification for application-specific
               instruction set processors},
  journal   = {Microprocessors and Microsystems - Embedded Hardware Design},
  volume    = {38},
  number    = {8},
  pages     = {1012--1024},
  year      = {2014},
  url       = {https://doi.org/10.1016/j.micpro.2014.09.001},
  doi       = {10.1016/j.micpro.2014.09.001},
  timestamp = {Thu, 18 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/mam/XiaoCWL14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/OlivaCMBDYRRM14,
  author    = {Yaset Oliva and
               Emmanuel Casseau and
               Kevin J. M. Martin and
               Pierre Bomel and
               Jean{-}Philippe Diguet and
               Herv{\'{e}} Yviquel and
               Micka{\"{e}}l Raulet and
               Erwan Raffin and
               Laurent Morin},
  title     = {Orcc's compa-backend demonstration},
  booktitle = {Proceedings of the 2014 Conference on Design and Architectures for
               Signal and Image Processing, {DASIP} 2014, Madrid, Spain, October
               8-10, 2014},
  pages     = {1--2},
  year      = {2014},
  crossref  = {DBLP:conf/dasip/2014},
  url       = {https://doi.org/10.1109/DASIP.2014.7115612},
  doi       = {10.1109/DASIP.2014.7115612},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/OlivaCMBDYRRM14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/YviquelSJTRC14,
  author    = {Herv{\'{e}} Yviquel and
               Alexandre Sanchez and
               Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
               Jarmo Takala and
               Micka{\"{e}}l Raulet and
               Emmanuel Casseau},
  title     = {Efficient software synthesis of dynamic dataflow programs},
  booktitle = {{IEEE} International Conference on Acoustics, Speech and Signal Processing,
               {ICASSP} 2014, Florence, Italy, May 4-9, 2014},
  pages     = {4988--4992},
  year      = {2014},
  crossref  = {DBLP:conf/icassp/2014},
  url       = {https://doi.org/10.1109/ICASSP.2014.6854551},
  doi       = {10.1109/ICASSP.2014.6854551},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icassp/YviquelSJTRC14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/XiaoC14,
  author    = {Chenglong Xiao and
               Emmanuel Casseau},
  title     = {Improving high-level synthesis effectiveness through custom operator
               identification},
  booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
               Melbourne, Victoria, Australia, June 1-5, 2014},
  pages     = {161--164},
  year      = {2014},
  crossref  = {DBLP:conf/iscas/2014},
  url       = {https://doi.org/10.1109/ISCAS.2014.6865090},
  doi       = {10.1109/ISCAS.2014.6865090},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/XiaoC14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/LeCC14,
  author    = {Quang Hoa Le and
               Emmanuel Casseau and
               Antoine Courtay},
  title     = {Place Reservation technique for online task placement on a multi-context
               heterogeneous reconfigurable architecture},
  booktitle = {2014 International Conference on ReConFigurable Computing and FPGAs,
               ReConFig14, Cancun, Mexico, December 8-10, 2014},
  pages     = {1--6},
  year      = {2014},
  crossref  = {DBLP:conf/reconfig/2014},
  url       = {https://doi.org/10.1109/ReConFig.2014.7032553},
  doi       = {10.1109/ReConFig.2014.7032553},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/reconfig/LeCC14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/spic/YviquelBRC13,
  author    = {Herv{\'{e}} Yviquel and
               Jani Boutellier and
               Micka{\"{e}}l Raulet and
               Emmanuel Casseau},
  title     = {Automated design of networks of transport-triggered architecture processors
               using dynamic dataflow programs},
  journal   = {Sig. Proc.: Image Comm.},
  volume    = {28},
  number    = {10},
  pages     = {1295--1302},
  year      = {2013},
  url       = {https://doi.org/10.1016/j.image.2013.08.013},
  doi       = {10.1016/j.image.2013.08.013},
  timestamp = {Mon, 06 Nov 2017 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/spic/YviquelBRC13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/imspa/YviquelCRJT13,
  author    = {Herv{\'{e}} Yviquel and
               Emmanuel Casseau and
               Micka{\"{e}}l Raulet and
               Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
               Jarmo Takala},
  title     = {Towards run-time actor mapping of dynamic dataflow programs onto multi-core
               platforms},
  booktitle = {8th International Symposium on Image and Signal Processing and Analysis,
               {ISPA} 2013, Trieste, Italy, September 4-6, 2013},
  pages     = {732--737},
  year      = {2013},
  crossref  = {DBLP:conf/imspa/2013},
  url       = {http://ieeexplore.ieee.org/xpl/freeabs\_all.jsp?arnumber=6703834},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/imspa/YviquelCRJT13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijertcs/RaffinWCCFKCG12,
  author    = {Erwan Raffin and
               Christophe Wolinski and
               Fran{\c{c}}ois Charot and
               Emmanuel Casseau and
               Antoine Floch and
               Krzysztof Kuchcinski and
               St{\'{e}}phane Chevobbe and
               St{\'{e}}phane Guyetant},
  title     = {Scheduling, Binding and Routing System for a Run-Time Reconfigurable
               Operator Based Multimedia Architecture},
  journal   = {{IJERTCS}},
  volume    = {3},
  number    = {1},
  pages     = {1--30},
  year      = {2012},
  url       = {https://doi.org/10.4018/jertcs.2012010101},
  doi       = {10.4018/jertcs.2012010101},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ijertcs/RaffinWCCFKCG12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CasseauG12,
  author    = {Emmanuel Casseau and
               Bertrand Le Gal},
  title     = {Design of multi-mode application-specific cores based on high-level
               synthesis},
  journal   = {Integration},
  volume    = {45},
  number    = {1},
  pages     = {9--21},
  year      = {2012},
  url       = {https://doi.org/10.1016/j.vlsi.2011.07.003},
  doi       = {10.1016/j.vlsi.2011.07.003},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/integration/CasseauG12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XiaoC12,
  author    = {Chenglong Xiao and
               Emmanuel Casseau},
  title     = {Exact custom instruction enumeration for extensible processors},
  journal   = {Integration},
  volume    = {45},
  number    = {3},
  pages     = {263--270},
  year      = {2012},
  url       = {https://doi.org/10.1016/j.vlsi.2011.11.011},
  doi       = {10.1016/j.vlsi.2011.11.011},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/integration/XiaoC12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ejasp/GalC11,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau},
  title     = {Latency-Sensitive High-Level Synthesis for Multiple Word-Length {DSP}
               Design},
  journal   = {{EURASIP} J. Adv. Sig. Proc.},
  volume    = {2011},
  year      = {2011},
  url       = {https://doi.org/10.1155/2011/927670},
  doi       = {10.1155/2011/927670},
  timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ejasp/GalC11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/GalC11,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau},
  title     = {Word-Length Aware {DSP} Hardware Design Flow Based on High-Level Synthesis},
  journal   = {Signal Processing Systems},
  volume    = {62},
  number    = {3},
  pages     = {341--357},
  year      = {2011},
  url       = {https://doi.org/10.1007/s11265-010-0467-8},
  doi       = {10.1007/s11265-010-0467-8},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/vlsisp/GalC11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/XiaoC11,
  author    = {Chenglong Xiao and
               Emmanuel Casseau},
  title     = {Efficient custom instruction enumeration for extensible processors},
  booktitle = {22nd {IEEE} International Conference on Application-specific Systems,
               Architectures and Processors, {ASAP} 2011, Santa Monica, CA, USA,
               Sept. 11-14, 2011},
  pages     = {211--214},
  year      = {2011},
  crossref  = {DBLP:conf/asap/2011},
  url       = {https://doi.org/10.1109/ASAP.2011.6043270},
  doi       = {10.1109/ASAP.2011.6043270},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asap/XiaoC11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/XiaoC11,
  author    = {Chenglong Xiao and
               Emmanuel Casseau},
  title     = {Efficient maximal convex custom instruction enumeration for extensible
               processors},
  booktitle = {2011 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2011, Tampere, Finland, November 2-4, 2011},
  pages     = {137--143},
  year      = {2011},
  crossref  = {DBLP:conf/dasip/2011},
  url       = {https://doi.org/10.1109/DASIP.2011.6136868},
  doi       = {10.1109/DASIP.2011.6136868},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/XiaoC11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/XiaoC11,
  author    = {Chenglong Xiao and
               Emmanuel Casseau},
  title     = {An efficient algorithm for custom instruction enumeration},
  booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
               Lausanne, Switzerland, May 2-6, 2011},
  pages     = {187--192},
  year      = {2011},
  crossref  = {DBLP:conf/glvlsi/2011},
  url       = {https://doi.org/10.1145/1973009.1973047},
  doi       = {10.1145/1973009.1973047},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/XiaoC11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/MenardNCGGRC11,
  author    = {Daniel M{\'{e}}nard and
               Hai{-}Nam Nguyen and
               Fran{\c{c}}ois Charot and
               St{\'{e}}phane Guyetant and
               J{\'{e}}r{\'{e}}mie Guillot and
               Erwan Raffin and
               Emmanuel Casseau},
  title     = {Exploiting reconfigurable {SWP} operators for multimedia applications},
  booktitle = {Proceedings of the {IEEE} International Conference on Acoustics, Speech,
               and Signal Processing, {ICASSP} 2011, May 22-27, 2011, Prague Congress
               Center, Prague, Czech Republic},
  pages     = {1717--1720},
  year      = {2011},
  crossref  = {DBLP:conf/icassp/2011},
  url       = {https://doi.org/10.1109/ICASSP.2011.5946832},
  doi       = {10.1109/ICASSP.2011.5946832},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icassp/MenardNCGGRC11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/BanciuCMM11,
  author    = {Andrei Banciu and
               Emmanuel Casseau and
               Daniel M{\'{e}}nard and
               Thierry Michel},
  title     = {Stochastic modeling for floating-point to fixed-point conversion},
  booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
               2011, October 4-7, 2011, Beirut, Lebanon},
  pages     = {180--185},
  year      = {2011},
  crossref  = {DBLP:conf/sips/2011},
  url       = {https://doi.org/10.1109/SiPS.2011.6088971},
  doi       = {10.1109/SiPS.2011.6088971},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/sips/BanciuCMM11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/YviquelCWR11,
  author    = {Herv{\'{e}} Yviquel and
               Emmanuel Casseau and
               Matthieu Wipliez and
               Micka{\"{e}}l Raulet},
  title     = {Efficient multicore scheduling of dataflow process networks},
  booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
               2011, October 4-7, 2011, Beirut, Lebanon},
  pages     = {198--203},
  year      = {2011},
  crossref  = {DBLP:conf/sips/2011},
  url       = {https://doi.org/10.1109/SiPS.2011.6088974},
  doi       = {10.1109/SiPS.2011.6088974},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/sips/YviquelCWR11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AndriamisainaCCC10,
  author    = {Caaliph Andriamisaina and
               Philippe Coussy and
               Emmanuel Casseau and
               Cyrille Chavet},
  title     = {High-Level Synthesis for Designing Multimode Architectures},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {29},
  number    = {11},
  pages     = {1736--1749},
  year      = {2010},
  url       = {https://doi.org/10.1109/TCAD.2010.2062751},
  doi       = {10.1109/TCAD.2010.2062751},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/AndriamisainaCCC10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/BanciuCMM10,
  author    = {Andrei Banciu and
               Emmanuel Casseau and
               Daniel M{\'{e}}nard and
               Thierry Michel},
  title     = {A case study of the stochastic modeling approach for range estimation},
  booktitle = {Proceedings of the 2010 Conference on Design {\&} Architectures
               for Signal {\&} Image Processing, {DASIP} 2010, Edinburgh, Scotland,
               UK, October 26-28, 2010, Electronic Chips {\&} Systems design
               Initiative, {ECSI}},
  pages     = {128--135},
  year      = {2010},
  crossref  = {DBLP:conf/dasip/2010},
  url       = {https://doi.org/10.1109/DASIP.2010.5706256},
  doi       = {10.1109/DASIP.2010.5706256},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/BanciuCMM10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/BeauminSCC10,
  author    = {Cecile Beaumin and
               Olivier Sentieys and
               Emmanuel Casseau and
               Arnaud Carer},
  title     = {A coarse-grain reconfigurable hardware architecture for RVC-CAL-based
               design},
  booktitle = {Proceedings of the 2010 Conference on Design {\&} Architectures
               for Signal {\&} Image Processing, {DASIP} 2010, Edinburgh, Scotland,
               UK, October 26-28, 2010, Electronic Chips {\&} Systems design
               Initiative, {ECSI}},
  pages     = {152--159},
  year      = {2010},
  crossref  = {DBLP:conf/dasip/2010},
  url       = {https://doi.org/10.1109/DASIP.2010.5706259},
  doi       = {10.1109/DASIP.2010.5706259},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/BeauminSCC10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dasip/RaffinWCKGCC10,
  author    = {Erwan Raffin and
               Christophe Wolinski and
               Fran{\c{c}}ois Charot and
               Krzysztof Kuchcinski and
               St{\'{e}}phane Guyetant and
               St{\'{e}}phane Chevobbe and
               Emmanuel Casseau},
  title     = {Scheduling, binding and routing system for a run-time reconfigurable
               operator based multimedia architecture},
  booktitle = {Proceedings of the 2010 Conference on Design {\&} Architectures
               for Signal {\&} Image Processing, {DASIP} 2010, Edinburgh, Scotland,
               UK, October 26-28, 2010, Electronic Chips {\&} Systems design
               Initiative, {ECSI}},
  pages     = {168--175},
  year      = {2010},
  crossref  = {DBLP:conf/dasip/2010},
  url       = {https://doi.org/10.1109/DASIP.2010.5706261},
  doi       = {10.1109/DASIP.2010.5706261},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/RaffinWCKGCC10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/MenardCKSCGD09,
  author    = {Daniel M{\'{e}}nard and
               Emmanuel Casseau and
               Shafqat Khan and
               Olivier Sentieys and
               St{\'{e}}phane Chevobbe and
               St{\'{e}}phane Guyetant and
               Rapha{\"{e}}l David},
  title     = {Reconfigurable Operator Based Multimedia Embedded Processor},
  booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 5th
               International Workshop, {ARC} 2009, Karlsruhe, Germany, March 16-18,
               2009. Proceedings},
  pages     = {39--49},
  year      = {2009},
  crossref  = {DBLP:conf/arc/2009},
  url       = {https://doi.org/10.1007/978-3-642-00641-8\_7},
  doi       = {10.1007/978-3-642-00641-8\_7},
  timestamp = {Fri, 19 Jul 2019 13:02:47 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/arc/MenardCKSCGD09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/KhanCM09,
  author    = {Shafqat Khan and
               Emmanuel Casseau and
               Daniel M{\'{e}}nard},
  title     = {Reconfigurable {SWP} Operator for Multimedia Processing},
  booktitle = {20th {IEEE} International Conference on Application-Specific Systems,
               Architectures and Processors, {ASAP} 2009, July 7-9, 2009, Boston,
               MA, {USA}},
  pages     = {199--202},
  year      = {2009},
  crossref  = {DBLP:conf/asap/2009},
  url       = {https://doi.org/10.1109/ASAP.2009.13},
  doi       = {10.1109/ASAP.2009.13},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asap/KhanCM09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/GalC09,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau},
  title     = {Automated multimode system design for high performance {DSP} applications},
  booktitle = {17th European Signal Processing Conference, {EUSIPCO} 2009, Glasgow,
               Scotland, UK, August 24-28, 2009},
  pages     = {1289--1293},
  year      = {2009},
  crossref  = {DBLP:conf/eusipco/2009},
  url       = {http://ieeexplore.ieee.org/document/7077444/},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/eusipco/GalC09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/CasseauG09,
  author    = {Emmanuel Casseau and
               Bertrand Le Gal},
  title     = {High-level synthesis for the design of FPGA-based signal processing
               systems},
  booktitle = {Proceedings of the 2009 International Conference on Embedded Computer
               Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2009),
               Samos, Greece, July 20-23, 2009},
  pages     = {25--32},
  year      = {2009},
  crossref  = {DBLP:conf/samos/2009ic},
  url       = {https://doi.org/10.1109/ICSAMOS.2009.5289238},
  doi       = {10.1109/ICSAMOS.2009.5289238},
  timestamp = {Thu, 25 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/samos/CasseauG09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsi/GalCA08,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau and
               Caaliph Andriamisaina},
  title     = {Synth{\`{e}}se de haut niveau tenant compte de la dynamique des traitements.
               Analyse de la largeur des donn{\'{e}}es d'applications du {TDSI}
               et gestion de cette information lors de la synth{\`{e}}se de haut
               niveau},
  journal   = {Technique et Science Informatiques},
  volume    = {27},
  number    = {9-10},
  pages     = {1129--1154},
  year      = {2008},
  url       = {https://doi.org/10.3166/tsi.27.1129-1154},
  doi       = {10.3166/tsi.27.1129-1154},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tsi/GalCA08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GalCH08,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau and
               Sylvain Huet},
  title     = {Dynamic Memory Access Management for High-Performance {DSP} Applications
               Using High-Level Synthesis},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {16},
  number    = {11},
  pages     = {1454--1464},
  year      = {2008},
  url       = {https://doi.org/10.1109/TVLSI.2008.2000821},
  doi       = {10.1109/TVLSI.2008.2000821},
  timestamp = {Thu, 18 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tvlsi/GalCH08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CoussyCBBM07,
  author    = {Philippe Coussy and
               Emmanuel Casseau and
               Pierre Bomel and
               Adel Baganne and
               Eric Martin},
  title     = {Constrained algorithmic {IP} design for system-on-chip},
  journal   = {Integration},
  volume    = {40},
  number    = {2},
  pages     = {94--105},
  year      = {2007},
  url       = {https://doi.org/10.1016/j.vlsi.2006.02.003},
  doi       = {10.1016/j.vlsi.2006.02.003},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/integration/CoussyCBBM07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/AndriamisainaCC07,
  author    = {Caaliph Andriamisaina and
               Emmanuel Casseau and
               Philippe Coussy},
  title     = {Synthesis of Multimode digital signal processing systems},
  booktitle = {Second {NASA/ESA} Conference on Adaptive Hardware and Systems {(AHS}
               2007), August 5-8, 2007, University of Edinburgh, Scotland, United
               Kingdom},
  pages     = {318--325},
  year      = {2007},
  crossref  = {DBLP:conf/ahs/2007},
  url       = {https://doi.org/10.1109/AHS.2007.100},
  doi       = {10.1109/AHS.2007.100},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ahs/AndriamisainaCC07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HuetLPC07,
  author    = {Sylvain Huet and
               S{\'{e}}bastien LeNours and
               Olivier Pasquier and
               Emmanuel Casseau},
  title     = {Granularity Issues in Transaction Level Modelling Digital Signal Processing
               Applications},
  booktitle = {Forum on specification and Design Languages, {FDL} 2007, September
               18-20, 2007, Barcelona, Spain, Proceedings},
  pages     = {177--184},
  year      = {2007},
  crossref  = {DBLP:conf/fdl/2007},
  url       = {http://www.ecsi-association.org/ecsi/main.asp?l1=library\&\#38;fn=def\&\#38;id=254},
  timestamp = {Sat, 26 Feb 2011 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fdl/HuetLPC07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChavetACCJUM07,
  author    = {Cyrille Chavet and
               Caaliph Andriamisaina and
               Philippe Coussy and
               Emmanuel Casseau and
               Emmanuel Juin and
               Pascal Urard and
               Eric Martin},
  title     = {A design flow dedicated to multi-mode architectures for {DSP} applications},
  booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
               San Jose, CA, USA, November 5-8, 2007},
  pages     = {604--611},
  year      = {2007},
  crossref  = {DBLP:conf/iccad/2007},
  url       = {https://doi.org/10.1109/ICCAD.2007.4397331},
  doi       = {10.1109/ICCAD.2007.4397331},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/ChavetACCJUM07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/GalBKC07,
  author    = {Bertrand Le Gal and
               Lilian Bossuet and
               Shafqat Khan and
               Emmanuel Casseau},
  title     = {{HLS} design flow for the synthesis of multimode systems under multiple
               constraints},
  booktitle = {14th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2007, Marrakech, Morocco, December 11-14, 2007},
  pages     = {314--317},
  year      = {2007},
  crossref  = {DBLP:conf/icecsys/2007},
  url       = {https://doi.org/10.1109/ICECS.2007.4510993},
  doi       = {10.1109/ICECS.2007.4510993},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icecsys/GalBKC07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigpro/SavatonCM06,
  author    = {Guillaume Savaton and
               Emmanuel Casseau and
               Eric Martin},
  title     = {Design of a flexible 2-D discrete wavelet transform {IP} core for
               {JPEG2000} image coding in embedded imaging systems},
  journal   = {Signal Processing},
  volume    = {86},
  number    = {7},
  pages     = {1375--1399},
  year      = {2006},
  url       = {https://doi.org/10.1016/j.sigpro.2005.03.022},
  doi       = {10.1016/j.sigpro.2005.03.022},
  timestamp = {Sun, 28 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/sigpro/SavatonCM06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/CoussyCBBM06,
  author    = {Philippe Coussy and
               Emmanuel Casseau and
               Pierre Bomel and
               Adel Baganne and
               Eric Martin},
  title     = {A formal method for hardware {IP} design and integration under {I/O}
               and timing constraints},
  journal   = {{ACM} Trans. Embedded Comput. Syst.},
  volume    = {5},
  number    = {1},
  pages     = {29--53},
  year      = {2006},
  url       = {https://doi.org/10.1145/1132357.1132359},
  doi       = {10.1145/1132357.1132359},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/tecs/CoussyCBBM06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/SayadiCAMTM06,
  author    = {Fatma Sayadi and
               Emmanuel Casseau and
               Mohamed Atri and
               Mehrez Marzougui and
               Rached Tourki and
               Eric Martin},
  title     = {{G729} Voice Decoder Design},
  journal   = {{VLSI} Signal Processing},
  volume    = {42},
  number    = {2},
  pages     = {173--184},
  year      = {2006},
  url       = {https://doi.org/10.1007/s11265-005-4180-y},
  doi       = {10.1007/s11265-005-4180-y},
  timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/vlsisp/SayadiCAMTM06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/HuetCP06,
  author    = {Sylvain Huet and
               Emmanuel Casseau and
               Olivier Pasquier},
  title     = {A Computation Core for Communication Refinement of Digital Signal
               Processing Algorithms},
  booktitle = {Ninth Euromicro Conference on Digital System Design: Architectures,
               Methods and Tools {(DSD} 2006), 30 August - 1 September 2006, Dubrovnik,
               Croatia},
  pages     = {240--250},
  year      = {2006},
  crossref  = {DBLP:conf/dsd/2006},
  url       = {https://doi.org/10.1109/DSD.2006.96},
  doi       = {10.1109/DSD.2006.96},
  timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dsd/HuetCP06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fdl/HuetCPL06,
  author    = {Sylvain Huet and
               Emmanuel Casseau and
               Olivier Pasquier and
               S{\'{e}}bastien LeNours},
  title     = {Hardware Communication Refinement in Digital Signal Processing},
  booktitle = {Forum on specification and Design Languages, {FDL} 2006, September
               19-22, 2006, Darmstadt, Germany, Proceedings},
  pages     = {177--185},
  year      = {2006},
  crossref  = {DBLP:conf/fdl/2006},
  url       = {http://www.ecsi-association.org/ecsi/main.asp?l1=library\&\#38;fn=def\&\#38;id=375},
  timestamp = {Sat, 26 Feb 2011 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fdl/HuetCPL06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/GalC06,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau},
  title     = {{IP} Generation Targeting Multiple Bit-Width Standards},
  booktitle = {13th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2006, Nice, France, December 10-13, 2006},
  pages     = {784--787},
  year      = {2006},
  crossref  = {DBLP:conf/icecsys/2006},
  url       = {https://doi.org/10.1109/ICECS.2006.379906},
  doi       = {10.1109/ICECS.2006.379906},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icecsys/GalC06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sips/AndriamisainaGC06,
  author    = {Caaliph Andriamisaina and
               Bertrand Le Gal and
               Emmanuel Casseau},
  title     = {Bit-Width Optimizations for High-Level Synthesis of Digital Signal
               Processing Systems},
  booktitle = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
               2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
  pages     = {280--285},
  year      = {2006},
  crossref  = {DBLP:conf/sips/2006},
  url       = {https://doi.org/10.1109/SIPS.2006.352595},
  doi       = {10.1109/SIPS.2006.352595},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/sips/AndriamisainaGC06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/GalAC06,
  author    = {Bertrand Le Gal and
               Caaliph Andriamisaina and
               Emmanuel Casseau},
  title     = {Bit-Width Aware High-Level Synthesis for Digital Signal Processing
               Systems},
  booktitle = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
               24-27, 2006},
  pages     = {175--178},
  year      = {2006},
  crossref  = {DBLP:conf/socc/2006},
  url       = {https://doi.org/10.1109/SOCC.2006.283875},
  doi       = {10.1109/SOCC.2006.283875},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/socc/GalAC06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/AbdelliBCFJKGH05,
  author    = {Nabil Abdelli and
               Pierre Bomel and
               Emmanuel Casseau and
               Anne{-}Marie Fouilliart and
               Christophe J{\'{e}}go and
               Philippe Kajfasz and
               Bertrand Le Gal and
               Nathalie Le Heno},
  title     = {Hardware Virtual Components Compliant with Communication System Standards},
  booktitle = {Eighth Euromicro Symposium on Digital Systems Design {(DSD} 2005),
               30 August - 3 September 2005, Porto, Portugal},
  pages     = {88--95},
  year      = {2005},
  crossref  = {DBLP:conf/dsd/2005},
  url       = {https://doi.org/10.1109/DSD.2005.44},
  doi       = {10.1109/DSD.2005.44},
  timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dsd/AbdelliBCFJKGH05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/CasseauGBJH005,
  author    = {Emmanuel Casseau and
               Bertrand Le Gal and
               Pierre Bomel and
               Christophe J{\'{e}}go and
               Sylvain Huet and
               Eric Martin},
  title     = {C-based rapid prototyping for digital signal processing},
  booktitle = {13th European Signal Processing Conference, {EUSIPCO} 2005, Antalya,
               Turkey, September 4-8, 2005},
  pages     = {1--4},
  year      = {2005},
  crossref  = {DBLP:conf/eusipco/2005},
  url       = {http://ieeexplore.ieee.org/document/7077970/},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/eusipco/CasseauGBJH005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eusipco/GalC005,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau and
               Eric Martin},
  title     = {Pipelined memory controllers for {DSP} real-time applications handling
               unpredictable data accesses},
  booktitle = {13th European Signal Processing Conference, {EUSIPCO} 2005, Antalya,
               Turkey, September 4-8, 2005},
  pages     = {1--4},
  year      = {2005},
  crossref  = {DBLP:conf/eusipco/2005},
  url       = {http://ieeexplore.ieee.org/document/7078210/},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/eusipco/GalC005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GalCHM05,
  author    = {Bertrand Le Gal and
               Emmanuel Casseau and
               Sylvain Huet and
               Eric Martin},
  title     = {Pipelined Memory Controllers for {DSP} Applications Handling Unpredictable
               Data Accesses},
  booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
               {USA}},
  pages     = {268--269},
  year      = {2005},
  crossref  = {DBLP:conf/isvlsi/2005},
  url       = {https://doi.org/10.1109/ISVLSI.2005.56},
  doi       = {10.1109/ISVLSI.2005.56},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/GalCHM05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/HuetCP05,
  author    = {Sylvain Huet and
               Emmanuel Casseau and
               Olivier Pasquier},
  title     = {Design Exploration and {HW/SW} Rapid Prototyping for Real-Time System
               Design},
  booktitle = {16th {IEEE} International Workshop on Rapid System Prototyping {(RSP}
               2005), 8-10 June 2005, Montreal, Canada},
  pages     = {240--243},
  year      = {2005},
  crossref  = {DBLP:conf/rsp/2005},
  url       = {https://doi.org/10.1109/RSP.2005.21},
  doi       = {10.1109/RSP.2005.21},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/rsp/HuetCP05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tsi/CasseauJM04,
  author    = {Emmanuel Casseau and
               Christophe J{\'{e}}go and
               Eric Martin},
  title     = {Synth{\`{e}}se architecturale d'applications temps r{\'{e}}el
               pour technologies submicroniques},
  journal   = {Technique et Science Informatiques},
  volume    = {23},
  number    = {1},
  pages     = {35--66},
  year      = {2004},
  url       = {https://doi.org/10.3166/tsi.23.35-66},
  doi       = {10.3166/tsi.23.35-66},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tsi/CasseauJM04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/CasseauGJHM04,
  author    = {Emmanuel Casseau and
               Bertrand Le Gal and
               Christophe J{\'{e}}go and
               Nathalie Le Heno and
               Eric Martin},
  title     = {Reed-Solomon behavioral virtual component for communication systems},
  booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  pages     = {173--176},
  year      = {2004},
  crossref  = {DBLP:conf/iscas/2004},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/CasseauGJHM04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/JegoCM99,
  author    = {Christophe J{\'{e}}go and
               Emmanuel Casseau and
               Eric Martin},
  title     = {Architectural Synthesis with Interconnection Cost Control},
  booktitle = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International
               Conference on Very Large Scale Integration {(VLSI} '99), December
               1-4, 1999, Lisbon, Portugal},
  pages     = {509--520},
  year      = {1999},
  crossref  = {DBLP:conf/ifip10-5/1999},
  timestamp = {Tue, 05 Jun 2012 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ifip10-5/JegoCM99},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LuthiC96,
  author    = {Eric Luthi and
               Emmanuel Casseau},
  title     = {High Rate Soft Output Viterbi Decoder},
  booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
               France, March 11-14, 1996},
  pages     = {315--319},
  year      = {1996},
  crossref  = {DBLP:conf/date/1996},
  url       = {https://doi.org/10.1109/EDTC.1996.494319},
  doi       = {10.1109/EDTC.1996.494319},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/date/LuthiC96},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/CasseauD94,
  author    = {Emmanuel Casseau and
               Dominique Degrugillier},
  title     = {A Linear Systolic Array for {LU} Decomposition},
  booktitle = {Proceedings of the Seventh International Conference on {VLSI} Design,
               {VLSI} Design 1994, Calcutta, India, January 5-8, 1994},
  pages     = {353--358},
  year      = {1994},
  crossref  = {DBLP:conf/vlsid/1994},
  url       = {https://doi.org/10.1109/ICVD.1994.282718},
  doi       = {10.1109/ICVD.1994.282718},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/CasseauD94},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2018,
  title     = {2018 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2018, Porto, Portugal, October 10-12, 2018},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8587115/proceeding},
  isbn      = {978-1-5386-8237-1},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/scopes/2018,
  editor    = {Sander Stuijk},
  title     = {Proceedings of the 21st International Workshop on Software and Compilers
               for Embedded Systems, {SCOPES} 2018, Sankt Goar, Germany, May 28-30,
               2018},
  publisher = {{ACM}},
  year      = {2018},
  url       = {http://dl.acm.org/citation.cfm?id=3207719},
  timestamp = {Mon, 11 Jun 2018 09:02:48 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/scopes/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2017,
  title     = {2017 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2017, Dresden, Germany, September 27-29, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/8114691/proceeding},
  isbn      = {978-1-5386-3534-6},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/crowncom/2016,
  editor    = {Dominique Noguet and
               Klaus Moessner and
               Jacques Palicot},
  title     = {Cognitive Radio Oriented Wireless Networks - 11th International Conference,
               {CROWNCOM} 2016, Grenoble, France, May 30 - June 1, 2016, Proceedings},
  series    = {Lecture Notes of the Institute for Computer Sciences, Social Informatics
               and Telecommunications Engineering},
  volume    = {172},
  publisher = {Springer},
  year      = {2016},
  url       = {https://doi.org/10.1007/978-3-319-40352-6},
  doi       = {10.1007/978-3-319-40352-6},
  isbn      = {978-3-319-40351-9},
  timestamp = {Fri, 19 May 2017 01:25:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/crowncom/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2016,
  title     = {2016 Conference on Design and Architectures for Signal and Image Processing
               (DASIP), Rennes, France, October 12-14, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7845248/proceeding},
  isbn      = {979-1-0922-7915-3},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2015,
  title     = {2015 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2015, Krakow, Poland, September 23-25, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7300013/proceeding},
  isbn      = {978-1-4673-7738-6},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2015,
  title     = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
               Montpellier, France, July 8-10, 2015},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7307713/proceeding},
  isbn      = {978-1-4799-8719-1},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2014,
  editor    = {Eduardo de la Torre and
               S{\'{e}}bastien Pillement},
  title     = {Proceedings of the 2014 Conference on Design and Architectures for
               Signal and Image Processing, {DASIP} 2014, Madrid, Spain, October
               8-10, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7108513/proceeding},
  isbn      = {979-10-92279-06-1},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2014},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/icassp/2014,
  title     = {{IEEE} International Conference on Acoustics, Speech and Signal Processing,
               {ICASSP} 2014, Florence, Italy, May 4-9, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6844297/proceeding},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icassp/2014},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2014,
  title     = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
               Melbourne, Victoria, Australia, June 1-5, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6852006/proceeding},
  isbn      = {978-1-4799-3431-7},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2014},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/reconfig/2014,
  title     = {2014 International Conference on ReConFigurable Computing and FPGAs,
               ReConFig14, Cancun, Mexico, December 8-10, 2014},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7012990/proceeding},
  isbn      = {978-1-4799-5944-0},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/reconfig/2014},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/imspa/2013,
  title     = {8th International Symposium on Image and Signal Processing and Analysis,
               {ISPA} 2013, Trieste, Italy, September 4-6, 2013},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6693156/proceeding},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/imspa/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asap/2011,
  editor    = {Joseph R. Cavallaro and
               Milos D. Ercegovac and
               Frank Hannig and
               Paolo Ienne and
               Earl E. Swartzlander Jr. and
               Alexandre F. Tenca},
  title     = {22nd {IEEE} International Conference on Application-specific Systems,
               Architectures and Processors, {ASAP} 2011, Santa Monica, CA, USA,
               Sept. 11-14, 2011},
  publisher = {{IEEE} Computer Society},
  year      = {2011},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6033675/proceeding},
  isbn      = {978-1-4577-1291-3},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asap/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2011,
  editor    = {Jari Nurmi and
               Tapani Ahonen},
  title     = {2011 Conference on Design and Architectures for Signal and Image Processing,
               {DASIP} 2011, Tampere, Finland, November 2-4, 2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6111682/proceeding},
  isbn      = {978-1-4577-0620-2},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2011,
  editor    = {David Atienza and
               Yuan Xie and
               Jos{\'{e}} L. Ayala and
               Ken S. Stevens},
  title     = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
               Lausanne, Switzerland, May 2-6, 2011},
  publisher = {{ACM}},
  year      = {2011},
  url       = {https://doi.org/10.1145/1973009},
  doi       = {10.1145/1973009},
  isbn      = {978-1-4503-0667-6},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/icassp/2011,
  title     = {Proceedings of the {IEEE} International Conference on Acoustics, Speech,
               and Signal Processing, {ICASSP} 2011, May 22-27, 2011, Prague Congress
               Center, Prague, Czech Republic},
  publisher = {{IEEE}},
  year      = {2011},
  isbn      = {978-1-4577-0539-7},
  timestamp = {Thu, 14 Jul 2011 10:50:58 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icassp/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/sips/2011,
  title     = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
               2011, October 4-7, 2011, Beirut, Lebanon},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/6086638/proceeding},
  isbn      = {978-1-4577-1920-2},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/sips/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dasip/2010,
  title     = {Proceedings of the 2010 Conference on Design {\&} Architectures
               for Signal {\&} Image Processing, {DASIP} 2010, Edinburgh, Scotland,
               UK, October 26-28, 2010, Electronic Chips {\&} Systems design
               Initiative, {ECSI}},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/5692849/proceeding},
  isbn      = {978-1-4244-8735-6},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dasip/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/arc/2009,
  editor    = {J{\"{u}}rgen Becker and
               Roger F. Woods and
               Peter M. Athanas and
               Fearghal Morgan},
  title     = {Reconfigurable Computing: Architectures, Tools and Applications, 5th
               International Workshop, {ARC} 2009, Karlsruhe, Germany, March 16-18,
               2009. Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {5453},
  publisher = {Springer},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00641-8},
  doi       = {10.1007/978-3-642-00641-8},
  isbn      = {978-3-642-00640-1},
  timestamp = {Fri, 19 Jul 2019 13:02:47 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/arc/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/asap/2009,
  title     = {20th {IEEE} International Conference on Application-Specific Systems,
               Architectures and Processors, {ASAP} 2009, July 7-9, 2009, Boston,
               MA, {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2009},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/5199994/proceeding},
  isbn      = {978-0-7695-3732-0},
  timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/asap/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/eusipco/2009,
  title     = {17th European Signal Processing Conference, {EUSIPCO} 2009, Glasgow,
               Scotland, UK, August 24-28, 2009},
  publisher = {{IEEE}},
  year      = {2009},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7077261/proceeding},
  isbn      = {978-161-7388-76-7},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/eusipco/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/samos/2009ic,
  editor    = {Walid A. Najjar and
               Michael J. Schulte},
  title     = {Proceedings of the 2009 International Conference on Embedded Computer
               Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2009),
               Samos, Greece, July 20-23, 2009},
  publisher = {{IEEE}},
  year      = {2009},
  isbn      = {978-1-4244-4501-1},
  timestamp = {Tue, 07 Sep 2010 07:45:33 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/samos/2009ic},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ahs/2007,
  editor    = {Tughrul Arslan and
               Adrian Stoica and
               Martin Suess and
               Didier Keymeulen and
               Tetsuya Higuchi and
               Ricardo Salem Zebulum and
               Ahmet T. Erdogan},
  title     = {Second {NASA/ESA} Conference on Adaptive Hardware and Systems {(AHS}
               2007), August 5-8, 2007, University of Edinburgh, Scotland, United
               Kingdom},
  publisher = {{IEEE} Computer Society},
  year      = {2007},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/4291882/proceeding},
  isbn      = {0-7695-2866-X},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ahs/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fdl/2007,
  title     = {Forum on specification and Design Languages, {FDL} 2007, September
               18-20, 2007, Barcelona, Spain, Proceedings},
  publisher = {{ECSI}},
  year      = {2007},
  timestamp = {Wed, 04 Mar 2009 14:27:08 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fdl/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/2007,
  editor    = {Georges G. E. Gielen},
  title     = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
               San Jose, CA, USA, November 5-8, 2007},
  publisher = {{IEEE} Computer Society},
  year      = {2007},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/4397222/proceeding},
  isbn      = {1-4244-1382-6},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/icecsys/2007,
  title     = {14th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2007, Marrakech, Morocco, December 11-14, 2007},
  publisher = {{IEEE}},
  year      = {2007},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/4456901/proceeding},
  isbn      = {978-1-4244-1377-5},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icecsys/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dsd/2006,
  title     = {Ninth Euromicro Conference on Digital System Design: Architectures,
               Methods and Tools {(DSD} 2006), 30 August - 1 September 2006, Dubrovnik,
               Croatia},
  publisher = {{IEEE} Computer Society},
  year      = {2006},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/11117/proceeding},
  isbn      = {0-7695-2609-8},
  timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dsd/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fdl/2006,
  title     = {Forum on specification and Design Languages, {FDL} 2006, September
               19-22, 2006, Darmstadt, Germany, Proceedings},
  publisher = {{ECSI}},
  year      = {2006},
  isbn      = {978-3-00-019710-9},
  timestamp = {Wed, 04 Mar 2009 14:23:41 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/fdl/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/icecsys/2006,
  title     = {13th {IEEE} International Conference on Electronics, Circuits, and
               Systems, {ICECS} 2006, Nice, France, December 10-13, 2006},
  publisher = {{IEEE}},
  year      = {2006},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/4263277/proceeding},
  isbn      = {1-4244-0395-2},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icecsys/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/sips/2006,
  title     = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
               2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
  publisher = {{IEEE}},
  year      = {2006},
  isbn      = {1-4244-0382-0},
  timestamp = {Fri, 11 Sep 2009 16:03:33 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/sips/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/socc/2006,
  title     = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
               24-27, 2006},
  publisher = {{IEEE}},
  year      = {2006},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/4062990/proceeding},
  isbn      = {0-7803-9781-9},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/socc/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/dsd/2005,
  title     = {Eighth Euromicro Symposium on Digital Systems Design {(DSD} 2005),
               30 August - 3 September 2005, Porto, Portugal},
  publisher = {{IEEE} Computer Society},
  year      = {2005},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/10433/proceeding},
  isbn      = {0-7695-2433-8},
  timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/dsd/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/eusipco/2005,
  title     = {13th European Signal Processing Conference, {EUSIPCO} 2005, Antalya,
               Turkey, September 4-8, 2005},
  publisher = {{IEEE}},
  year      = {2005},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/7077326/proceeding},
  isbn      = {978-160-4238-21-1},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/eusipco/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2005,
  title     = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
               {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2005},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/9780/proceeding},
  isbn      = {0-7695-2365-X},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/rsp/2005,
  title     = {16th {IEEE} International Workshop on Rapid System Prototyping {(RSP}
               2005), 8-10 June 2005, Montreal, Canada},
  publisher = {{IEEE} Computer Society},
  year      = {2005},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/10092/proceeding},
  isbn      = {0-7695-2361-7},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/rsp/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2004,
  title     = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  publisher = {{IEEE}},
  year      = {2004},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/9255/proceeding},
  isbn      = {0-7803-8251-X},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2004},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ifip10-5/1999,
  editor    = {L. Miguel Silveira and
               Srinivas Devadas and
               Ricardo Augusto da Luz Reis},
  title     = {{VLSI:} Systems on a Chip, {IFIP} {TC10/WG10.5} Tenth International
               Conference on Very Large Scale Integration {(VLSI} '99), December
               1-4, 1999, Lisbon, Portugal},
  series    = {{IFIP} Conference Proceedings},
  volume    = {162},
  publisher = {Kluwer},
  year      = {2000},
  isbn      = {0-7923-7731-1},
  timestamp = {Mon, 14 Oct 2002 13:30:59 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ifip10-5/1999},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/date/1996,
  title     = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
               France, March 11-14, 1996},
  publisher = {{IEEE} Computer Society},
  year      = {1996},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/3563/proceeding},
  isbn      = {0-8186-7423-7},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/date/1996},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsid/1994,
  title     = {Proceedings of the Seventh International Conference on {VLSI} Design,
               {VLSI} Design 1994, Calcutta, India, January 5-8, 1994},
  publisher = {{IEEE} Computer Society},
  year      = {1994},
  url       = {https://ieeexplore.ieee.org/xpl/conhome/930/proceeding},
  isbn      = {0-8186-4990-9},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/1994},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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