default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Yuen H. Chan
@article{DBLP:journals/ibmrd/WolpertBSCTBSVA18,
author = {David Wolpert and
Erwin Behnen and
Leon J. Sigal and
Yuen H. Chan and
Gustavo Enrique T{\'{e}}llez and
Douglas Bradley and
Richard E. Serton and
Rajesh Veerabhadraiah and
William Ansley and
Andrew Bianchi and
Nagu Dhanwada and
Sungjae Lee and
Michael Scheuermann and
Glen A. Wiedemeier and
John Davis and
Tobias Werner and
Laura Darden and
Keith G. Barkley and
Michael Gray and
Matthew Guzowski and
Mitch DeHond and
Timothy Schell and
Stelios Tsapepas and
Di Phan and
Kriti Acharya and
Jeffrey A. Zitz and
Hunter F. Shi and
Christopher J. Berry and
James D. Warnock and
Michael H. Wood and
Robert M. Averill III},
title = {{IBM} z14: Enabling physical design in 14-nm technology for high-performance,
high-reliability microprocessors},
journal = {{IBM} J. Res. Dev.},
volume = {62},
number = {2/3},
pages = {10:1--10:14},
year = {2018},
url = {https://doi.org/10.1147/JRD.2018.2800499},
doi = {10.1147/JRD.2018.2800499},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ibmrd/WolpertBSCTBSVA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockCBFPCCSS15,
author = {James D. Warnock and
Brian W. Curran and
John Badar and
Gregory Fredeman and
Donald W. Plass and
Yuen H. Chan and
Sean M. Carey and
Gerard Salem and
Friedrich Schroeder and
Frank Malgioglio and
Guenter Mayer and
Christopher J. Berry and
Michael H. Wood and
Yiu{-}Hing Chan and
Mark D. Mayo and
John Isakson and
Charudhattan Nagarajan and
Tobias Werner and
Leon J. Sigal and
Ricardo Nigaglioni and
Mark Cichanowski and
Jeffrey A. Zitz and
Matthew M. Ziegler and
Tim Bronson and
Gerald Strevig and
Daniel Dreps and
Ruchir Puri and
Douglas Malone and
Dieter F. Wendel and
Pak{-}kin Mak and
Michael A. Blake},
title = {4.1 22nm Next-generation {IBM} System z microprocessor},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062930},
doi = {10.1109/ISSCC.2015.7062930},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WarnockCBFPCCSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WarnockCHCSMPZJSDGBMCMRSSSWMSPW14,
author = {James D. Warnock and
Yuen H. Chan and
Hubert Harrer and
Sean M. Carey and
Gerard Salem and
Doug Malone and
Ruchir Puri and
Jeffrey A. Zitz and
Adam Jatkowski and
Gerald Strevig and
Ayan Datta and
Anne Gattiker and
Aditya Bansal and
Guenter Mayer and
Yiu{-}Hing Chan and
Mark D. Mayo and
David L. Rude and
Leon J. Sigal and
Thomas Strach and
Howard H. Smith and
Huajun Wen and
Pak{-}kin Mak and
Chung{-}Lung Kevin Shum and
Donald W. Plass and
Charles F. Webb},
title = {Circuit and Physical Design of the zEnterprise{\texttrademark} {EC12}
Microprocessor Chips and Multi-Chip Module},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {1},
pages = {9--18},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2284647},
doi = {10.1109/JSSC.2013.2284647},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WarnockCHCSMPZJSDGBMCMRSSSWMSPW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockCHRPCSMCMJSSDGBMSWMSPW13,
author = {James D. Warnock and
Yuen H. Chan and
Hubert Harrer and
David L. Rude and
Ruchir Puri and
Sean M. Carey and
Gerard Salem and
Guenter Mayer and
Yiu{-}Hing Chan and
Mark D. Mayo and
Adam Jatkowski and
Gerald Strevig and
Leon J. Sigal and
Ayan Datta and
Anne Gattiker and
Aditya Bansal and
Doug Malone and
Thomas Strach and
Huajun Wen and
Pak{-}kin Mak and
Chung{-}Lung Kevin Shum and
Donald W. Plass and
Charles F. Webb},
title = {5.5GHz system z microprocessor and multi-chip module},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {46--47},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487630},
doi = {10.1109/ISSCC.2013.6487630},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WarnockCHRPCSMCMJSSDGBMSWMSPW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DavisBHCSRPKW13,
author = {John Davis and
Paul Bunce and
Diana M. Henderson and
Yuen H. Chan and
Uma Srinivasan and
Daniel Rodko and
Pradip Patel and
Thomas J. Knips and
Tobias Werner},
title = {7GHz {L1} cache SRAMs for the 32nm zEnterprise{\texttrademark} {EC12}
processor},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {324--325},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487754},
doi = {10.1109/ISSCC.2013.6487754},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DavisBHCSRPKW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WarnockCCWMGSCDBPRPSMMNRH12,
author = {James D. Warnock and
Yiu{-}Hing Chan and
Sean M. Carey and
Huajun Wen and
Patrick J. Meaney and
Guenter Gerwig and
Howard H. Smith and
Yuen H. Chan and
John Davis and
Paul Bunce and
Antonio Pelella and
Daniel Rodko and
Pradip Patel and
Thomas Strach and
Doug Malone and
Frank Malgioglio and
Jos{\'{e}} Neves and
David L. Rude and
William V. Huott},
title = {Circuit and Physical Design Implementation of the Microprocessor Chip
for the zEnterprise System},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {1},
pages = {151--163},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2011.2169308},
doi = {10.1109/JSSC.2011.2169308},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WarnockCCWMGSCDBPRPSMMNRH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockCHCFWSMMPCMMSRAWSSCSEMWMMW11,
author = {James D. Warnock and
Y. Chan and
William V. Huott and
Sean M. Carey and
Michael F. Fee and
Huajun Wen and
Mary Jo Saccamango and
Frank Malgioglio and
Patrick J. Meaney and
Donald W. Plass and
Yuen H. Chan and
Mark D. Mayo and
Guenter Mayer and
Leon J. Sigal and
David L. Rude and
Robert M. Averill III and
Michael H. Wood and
Thomas Strach and
Howard H. Smith and
Brian W. Curran and
Eric M. Schwarz and
Lee Eisen and
Doug Malone and
Steve Weitzel and
Pak{-}kin Mak and
Thomas J. McPherson and
Charles F. Webb},
title = {A 5.2GHz microprocessor chip for the {IBM} zEnterprise{\texttrademark}
system},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {70--72},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746223},
doi = {10.1109/ISSCC.2011.5746223},
timestamp = {Thu, 07 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WarnockCHCFWSMMPCMMSRAWSSCSEMWMMW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/PelellaCBPRS11,
author = {Antonio Pelella and
Yuen H. Chan and
Bargav Balakrishnan and
Pradip Patel and
Daniel Rodko and
Richard E. Serton},
title = {Dynamic hit logic with embedded 8Kb {SRAM} in 45nm {SOI} for the zEnterprise{\texttrademark}
processor},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {72--73},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746224},
doi = {10.1109/ISSCC.2011.5746224},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/PelellaCBPRS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/JoshiKPTC10,
author = {Rajiv V. Joshi and
Rouwaida Kanj and
Anthony Pelella and
Arthur Tuminaro and
Yuen H. Chan},
title = {The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory
Lane},
journal = {{IEEE} Des. Test Comput.},
volume = {27},
number = {6},
pages = {36--45},
year = {2010},
url = {https://doi.org/10.1109/MDT.2010.95},
doi = {10.1109/MDT.2010.95},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/JoshiKPTC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JoshiMPCCT09,
author = {Rajiv V. Joshi and
Saibal Mukhopadhyay and
Donald W. Plass and
Yuen H. Chan and
Ching{-}Te Chuang and
Yue Tan},
title = {Design of Sub-90 nm Low-Power and Variation Tolerant {PD/SOI} {SRAM}
Cell Based on Dynamic Stability Metrics},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {3},
pages = {965--976},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2013768},
doi = {10.1109/JSSC.2009.2013768},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JoshiMPCCT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BhavnagarwalaKR08,
author = {Azeez J. Bhavnagarwala and
Stephen Kosonocky and
Carl Radens and
Yuen H. Chan and
Kevin Stawiasz and
Uma Srinivasan and
Steven P. Kowalczyk and
Matthew M. Ziegler},
title = {A Sub-600-mV, Fluctuation Tolerant 65-nm {CMOS} {SRAM} Array With
Dynamic Cell Biasing},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {4},
pages = {946--955},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2008.917506},
doi = {10.1109/JSSC.2008.917506},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BhavnagarwalaKR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/PlassC07,
author = {Donald W. Plass and
Yuen H. Chan},
title = {{IBM} {POWER6} {SRAM} arrays},
journal = {{IBM} J. Res. Dev.},
volume = {51},
number = {6},
pages = {747--756},
year = {2007},
url = {https://doi.org/10.1147/rd.516.0747},
doi = {10.1147/RD.516.0747},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/PlassC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FriedrichMJHCFMCCPCLCRTDL07,
author = {Joshua Friedrich and
Bradley D. McCredie and
Norman K. James and
Bill Huott and
Brian W. Curran and
Eric Fluhr and
Gaurav Mittal and
Eddie Chan and
Yuen H. Chan and
Donald W. Plass and
Sam G. Chu and
Hung Q. Le and
Leo Clark and
John R. Ripley and
Scott A. Taylor and
Jack DiLullo and
Mary Yvonne Lanzerotti},
title = {Design of the Power6 Microprocessor},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {96--97},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373605},
doi = {10.1109/ISSCC.2007.373605},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FriedrichMJHCFMCCPCLCRTDL07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/CurranMSSFCWVG06,
author = {Brian W. Curran and
Bradley D. McCredie and
Leonid Sigal and
Eric M. Schwarz and
Bruce M. Fleischer and
Yuen H. Chan and
D. Webber and
Vaden Vaden and
A. Goyal},
title = {4GHz+ low-latency fixed-point and binary floating-point execution
units for the {POWER6} processor},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {1728--1734},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696229},
doi = {10.1109/ISSCC.2006.1696229},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/isscc/CurranMSSFCWVG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DavisPBCPJCHKPL06,
author = {John Davis and
Don Plass and
Paul Bunce and
Yuen H. Chan and
Antonio Pelella and
Rajiv V. Joshi and
A. Chen and
William V. Huott and
Thomas J. Knips and
Pradip Patel and
K. Lo and
Eric Fluhr},
title = {A 5.6GHz 64kB Dual-Read Data Cache for the {POWER6TM} Processor},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {2564--2571},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696322},
doi = {10.1109/ISSCC.2006.1696322},
timestamp = {Tue, 09 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DavisPBCPJCHKPL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/PelellaTFC05,
author = {Antonio Pelella and
Arthur Tuminaro and
Ryan T. Freese and
Yuen H. Chan},
editor = {Laurent Fesquet and
Andreas Kaiser and
Sorin Cristoloveanu and
Michel Brillou{\"{e}}t},
title = {A 8Kb domino read {SRAM} with hit logic and parity checker},
booktitle = {Proceedings of the 31st European Solid-State Circuits Conference,
{ESSCIRC} 2005, Grenoble, France, 12-16 September 2005},
pages = {359--362},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ESSCIR.2005.1541634},
doi = {10.1109/ESSCIR.2005.1541634},
timestamp = {Fri, 28 Apr 2023 15:39:25 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/PelellaTFC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/JoshiC05,
author = {Rajiv V. Joshi and
Yuen H. Chan},
editor = {Laurent Fesquet and
Andreas Kaiser and
Sorin Cristoloveanu and
Michel Brillou{\"{e}}t},
title = {A novel circuit topology for generating and validating digitally sense
amplifier differentials for bulk and {SOI}},
booktitle = {Proceedings of the 31st European Solid-State Circuits Conference,
{ESSCIRC} 2005, Grenoble, France, 12-16 September 2005},
pages = {371--374},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ESSCIR.2005.1541637},
doi = {10.1109/ESSCIR.2005.1541637},
timestamp = {Fri, 28 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/JoshiC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SongSHWSCRNEMTWM05,
author = {Peilin Song and
Franco Stellari and
Bill Huott and
Otto Wagner and
Uma Srinivasan and
Yuen H. Chan and
Rick Rizzolo and
H. J. Nam and
James P. Eckhardt and
Timothy G. McNamara and
Ching{-}Lung Tong and
Alan J. Weger and
Moyra K. McManus},
title = {An advanced optical diagnostic technique of {IBM} z990 eServer microprocessor},
booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,
Austin, TX, USA, November 8-10, 2005},
pages = {9},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/TEST.2005.1584091},
doi = {10.1109/TEST.2005.1584091},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/SongSHWSCRNEMTWM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/JoshiMPCCD04,
author = {Rajiv V. Joshi and
Saibal Mukhopadhyay and
Donald W. Plass and
Yuen H. Chan and
Ching{-}Te Chuang and
Anirudh Devgan},
editor = {Michiel Steyaert and
C. L. Claeys},
title = {Variability analysis for sub-100 nm {PD/SOI} {CMOS} {SRAM} cell},
booktitle = {33rd European Solid-State Circuits Conference, {ESSCIRC} 2004, Leuven,
Belgium, September 21-23, 2004},
pages = {211--214},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ESSCIR.2004.1356655},
doi = {10.1109/ESSCIR.2004.1356655},
timestamp = {Wed, 29 Mar 2023 10:59:49 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/JoshiMPCCD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/CurranCWCNHLEHS02,
author = {Brian W. Curran and
Yuen H. Chan and
Philip T. Wu and
Peter J. Camporese and
Gregory A. Northrop and
Robert F. Hatch and
Lisa B. Lacey and
James P. Eckhardt and
David T. Hui and
Howard H. Smith},
title = {{IBM} eServer z900 high-frequency microprocessor technology, circuits,
and design methodology},
journal = {{IBM} J. Res. Dev.},
volume = {46},
number = {4-5},
pages = {631},
year = {2002},
url = {https://doi.org/10.1147/rd.464.0631},
doi = {10.1147/RD.464.0631},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/CurranCWCNHLEHS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/HuottMKSMSWCPP99,
author = {William V. Huott and
Moyra K. McManus and
Daniel R. Knebel and
Steve Steen and
Dennis Manzer and
Pia N. Sanda and
Steven C. Wilson and
Yuen H. Chan and
Antonio Pelella and
Stanislav Polonsky},
title = {The attack of the "Holey Shmoos": a case study of advanced
{DFD} and picosecond imaging circuit analysis {(PICA)}},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {883--891},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805820},
doi = {10.1109/TEST.1999.805820},
timestamp = {Fri, 23 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/HuottMKSMSWCPP99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/HoffmanACCDHMMNSPW98,
author = {Dale E. Hoffman and
Robert M. Averill III and
Brian W. Curran and
Yuen H. Chan and
Allan H. Dansky and
Robert F. Hatch and
Timothy G. McNamara and
Thomas J. McPherson and
Gregory A. Northrop and
Leon J. Sigal and
Anthony Pelella and
Patrick M. Williams},
title = {Deep submicron design techniques for the 500 MHz {IBM} {S/390} {G5}
custom microprocessor},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {258--263},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727059},
doi = {10.1109/ICCD.1998.727059},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/HoffmanACCDHMMNSPW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/SigalWCCCMHKCEW97,
author = {Leon J. Sigal and
James D. Warnock and
Brian W. Curran and
Yuen H. Chan and
Peter J. Camporese and
Mark D. Mayo and
William V. Huott and
Daniel R. Knebel and
Ching{-}Te Chuang and
James P. Eckhardt and
Philip T. Wu},
title = {Circuit design techniques for the high-performance {CMOS} {IBM} {S/390}
Parallel Enterprise Server {G4} microprocessor},
journal = {{IBM} J. Res. Dev.},
volume = {41},
number = {4{\&}5},
pages = {489--504},
year = {1997},
url = {https://doi.org/10.1147/rd.414.0489},
doi = {10.1147/RD.414.0489},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/SigalWCCCMHKCEW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WebbASSLWCKMCSF97,
author = {Charles F. Webb and
Carl J. Anderson and
Leon J. Sigal and
Kenneth L. Shepard and
John S. Liptay and
James D. Warnock and
Brian W. Curran and
Barry Krumm and
Mark D. Mayo and
Peter J. Camporese and
Eric M. Schwarz and
Mark S. Farrell and
Phillip J. Restle and
Robert M. Averill III and
Timothy J. Slegel and
William V. Huott and
Yuen H. Chan and
Bruce Wile and
Thao N. Nguyen and
Philip G. Emma and
Daniel K. Beece and
Ching{-}Te Chuang and
Cyril Price},
title = {A 4.1-ns compact 54{\texttimes}54-b multiplier utilizing sign-select
Booth encoders},
journal = {{IEEE} J. Solid State Circuits},
volume = {32},
number = {11},
pages = {1676--1682},
year = {1997},
url = {https://doi.org/10.1109/4.641687},
doi = {10.1109/4.641687},
timestamp = {Tue, 26 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WebbASSLWCKMCSF97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/WarnockSCC97,
author = {James D. Warnock and
Leon J. Sigal and
Brian W. Curran and
Yuen H. Chan},
title = {High-Performance {CMOS} Circuit Techniques for the {G-4} {S/390} Microprocessor},
booktitle = {Proceedings 1997 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
October 12-15, 1997},
pages = {247--252},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ICCD.1997.628875},
doi = {10.1109/ICCD.1997.628875},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/WarnockSCC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/ReohrCPPW93,
author = {William R. Reohr and
Yuen H. Chan and
Donald W. Plass and
Antonio Pelella and
Philip T. Wu},
title = {Design SRAMs for burn-in},
booktitle = {11th {IEEE} {VLSI} Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993,
Atlantic City, NJ, {USA}},
pages = {164--170},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/VTEST.1993.313330},
doi = {10.1109/VTEST.1993.313330},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/ReohrCPPW93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-08-25 19:15 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
