BibTeX records: Brian W. Curran

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@article{DBLP:journals/jssc/LeeASZKVCFGCMOL22,
  author       = {Sae Kyu Lee and
                  Ankur Agrawal and
                  Joel Silberman and
                  Matthew M. Ziegler and
                  Mingu Kang and
                  Swagath Venkataramani and
                  Nianzheng Cao and
                  Bruce M. Fleischer and
                  Michael Guillorn and
                  Matthew Cohen and
                  Silvia M. Mueller and
                  Jinwook Oh and
                  Martin Lutz and
                  Jinwook Jung and
                  Siyu Koswatta and
                  Ching Zhou and
                  Vidhi Zalani and
                  Monodeep Kar and
                  James Bonanno and
                  Robert Casatuta and
                  Chia{-}Yu Chen and
                  Jungwook Choi and
                  Howard Haynie and
                  Alyssa Herbert and
                  Radhika Jain and
                  Kyu{-}Hyoun Kim and
                  Yulong Li and
                  Zhibin Ren and
                  Scot Rider and
                  Marcel Schaal and
                  Kerstin Schelm and
                  Michael Scheuermann and
                  Xiao Sun and
                  Hung Tran and
                  Naigang Wang and
                  Wei Wang and
                  Xin Zhang and
                  Vinay Shah and
                  Brian W. Curran and
                  Vijayalakshmi Srinivasan and
                  Pong{-}Fei Lu and
                  Sunil Shukla and
                  Kailash Gopalakrishnan and
                  Leland Chang},
  title        = {A 7-nm Four-Core Mixed-Precision {AI} Chip With 26.2-TFLOPS Hybrid-FP8
                  Training, 104.9-TOPS {INT4} Inference, and Workload-Aware Throttling},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {57},
  number       = {1},
  pages        = {182--197},
  year         = {2022},
  url          = {https://doi.org/10.1109/JSSC.2021.3120113},
  doi          = {10.1109/JSSC.2021.3120113},
  timestamp    = {Sat, 19 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LeeASZKVCFGCMOL22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/VenkataramaniSW21,
  author       = {Swagath Venkataramani and
                  Vijayalakshmi Srinivasan and
                  Wei Wang and
                  Sanchari Sen and
                  Jintao Zhang and
                  Ankur Agrawal and
                  Monodeep Kar and
                  Shubham Jain and
                  Alberto Mannari and
                  Hoang Tran and
                  Yulong Li and
                  Eri Ogawa and
                  Kazuaki Ishizaki and
                  Hiroshi Inoue and
                  Marcel Schaal and
                  Mauricio J. Serrano and
                  Jungwook Choi and
                  Xiao Sun and
                  Naigang Wang and
                  Chia{-}Yu Chen and
                  Allison Allain and
                  James Bonanno and
                  Nianzheng Cao and
                  Robert Casatuta and
                  Matthew Cohen and
                  Bruce M. Fleischer and
                  Michael Guillorn and
                  Howard Haynie and
                  Jinwook Jung and
                  Mingu Kang and
                  Kyu{-}Hyoun Kim and
                  Siyu Koswatta and
                  Sae Kyu Lee and
                  Martin Lutz and
                  Silvia M. Mueller and
                  Jinwook Oh and
                  Ashish Ranjan and
                  Zhibin Ren and
                  Scot Rider and
                  Kerstin Schelm and
                  Michael Scheuermann and
                  Joel Silberman and
                  Jie Yang and
                  Vidhi Zalani and
                  Xin Zhang and
                  Ching Zhou and
                  Matthew M. Ziegler and
                  Vinay Shah and
                  Moriyoshi Ohara and
                  Pong{-}Fei Lu and
                  Brian W. Curran and
                  Sunil Shukla and
                  Leland Chang and
                  Kailash Gopalakrishnan},
  title        = {RaPiD: {AI} Accelerator for Ultra-low Precision Training and Inference},
  booktitle    = {48th {ACM/IEEE} Annual International Symposium on Computer Architecture,
                  {ISCA} 2021, Virtual Event / Valencia, Spain, June 14-18, 2021},
  pages        = {153--166},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISCA52012.2021.00021},
  doi          = {10.1109/ISCA52012.2021.00021},
  timestamp    = {Mon, 19 Feb 2024 07:32:07 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/VenkataramaniSW21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AgrawalLSZKVCFG21,
  author       = {Ankur Agrawal and
                  Sae Kyu Lee and
                  Joel Silberman and
                  Matthew M. Ziegler and
                  Mingu Kang and
                  Swagath Venkataramani and
                  Nianzheng Cao and
                  Bruce M. Fleischer and
                  Michael Guillorn and
                  Matt Cohen and
                  Silvia M. Mueller and
                  Jinwook Oh and
                  Martin Lutz and
                  Jinwook Jung and
                  Siyu Koswatta and
                  Ching Zhou and
                  Vidhi Zalani and
                  James Bonanno and
                  Robert Casatuta and
                  Chia{-}Yu Chen and
                  Jungwook Choi and
                  Howard Haynie and
                  Alyssa Herbert and
                  Radhika Jain and
                  Monodeep Kar and
                  Kyu{-}Hyoun Kim and
                  Yulong Li and
                  Zhibin Ren and
                  Scot Rider and
                  Marcel Schaal and
                  Kerstin Schelm and
                  Michael Scheuermann and
                  Xiao Sun and
                  Hung Tran and
                  Naigang Wang and
                  Wei Wang and
                  Xin Zhang and
                  Vinay Shah and
                  Brian W. Curran and
                  Vijayalakshmi Srinivasan and
                  Pong{-}Fei Lu and
                  Sunil Shukla and
                  Leland Chang and
                  Kailash Gopalakrishnan},
  title        = {A 7nm 4-Core {AI} Chip with 25.6TFLOPS Hybrid {FP8} Training, 102.4TOPS
                  {INT4} Inference and Workload-Aware Throttling},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {144--146},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9365791},
  doi          = {10.1109/ISSCC42613.2021.9365791},
  timestamp    = {Sat, 19 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/AgrawalLSZKVCFG21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/VenkataramaniSW20,
  author       = {Swagath Venkataramani and
                  Xiao Sun and
                  Naigang Wang and
                  Chia{-}Yu Chen and
                  Jungwook Choi and
                  Mingu Kang and
                  Ankur Agarwal and
                  Jinwook Oh and
                  Shubham Jain and
                  Tina Babinsky and
                  Nianzheng Cao and
                  Thomas W. Fox and
                  Bruce M. Fleischer and
                  George Gristede and
                  Michael Guillorn and
                  Howard Haynie and
                  Hiroshi Inoue and
                  Kazuaki Ishizaki and
                  Michael J. Klaiber and
                  Shih{-}Hsien Lo and
                  Gary W. Maier and
                  Silvia M. Mueller and
                  Michael Scheuermann and
                  Eri Ogawa and
                  Marcel Schaal and
                  Mauricio J. Serrano and
                  Joel Silberman and
                  Christos Vezyrtzis and
                  Wei Wang and
                  Fanchieh Yee and
                  Jintao Zhang and
                  Matthew M. Ziegler and
                  Ching Zhou and
                  Moriyoshi Ohara and
                  Pong{-}Fei Lu and
                  Brian W. Curran and
                  Sunil Shukla and
                  Vijayalakshmi Srinivasan and
                  Leland Chang and
                  Kailash Gopalakrishnan},
  title        = {Efficient {AI} System Design With Cross-Layer Approximate Computing},
  journal      = {Proc. {IEEE}},
  volume       = {108},
  number       = {12},
  pages        = {2232--2250},
  year         = {2020},
  url          = {https://doi.org/10.1109/JPROC.2020.3029453},
  doi          = {10.1109/JPROC.2020.3029453},
  timestamp    = {Sat, 19 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/pieee/VenkataramaniSW20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/OhLKZSAVFGCWMBB20,
  author       = {Jinwook Oh and
                  Sae Kyu Lee and
                  Mingu Kang and
                  Matthew M. Ziegler and
                  Joel Silberman and
                  Ankur Agrawal and
                  Swagath Venkataramani and
                  Bruce M. Fleischer and
                  Michael Guillorn and
                  Jungwook Choi and
                  Wei Wang and
                  Silvia M. Mueller and
                  Shimon Ben{-}Yehuda and
                  James Bonanno and
                  Nianzheng Cao and
                  Robert Casatuta and
                  Chia{-}Yu Chen and
                  Matt Cohen and
                  Ophir Erez and
                  Thomas W. Fox and
                  George Gristede and
                  Howard Haynie and
                  Vicktoria Ivanov and
                  Siyu Koswatta and
                  Shih{-}Hsien Lo and
                  Martin Lutz and
                  Gary W. Maier and
                  Alex Mesh and
                  Yevgeny Nustov and
                  Scot Rider and
                  Marcel Schaal and
                  Michael Scheuermann and
                  Xiao Sun and
                  Naigang Wang and
                  Fanchieh Yee and
                  Ching Zhou and
                  Vinay Shah and
                  Brian W. Curran and
                  Vijayalakshmi Srinivasan and
                  Pong{-}Fei Lu and
                  Sunil Shukla and
                  Kailash Gopalakrishnan and
                  Leland Chang},
  title        = {A 3.0 {TFLOPS} 0.62V Scalable Processor Core for High Compute Utilization
                  {AI} Training and Inference},
  booktitle    = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
                  HI, USA, June 16-19, 2020},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/VLSICircuits18222.2020.9162917},
  doi          = {10.1109/VLSICIRCUITS18222.2020.9162917},
  timestamp    = {Sat, 19 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/OhLKZSAVFGCWMBB20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SrinivasanFSZSO18,
  author       = {Vijayalakshmi Srinivasan and
                  Bruce M. Fleischer and
                  Sunil Shukla and
                  Matthew M. Ziegler and
                  Joel Silberman and
                  Jinwook Oh and
                  Jungwook Choi and
                  Silvia M. Mueller and
                  Ankur Agrawal and
                  Tina Babinsky and
                  Nianzheng Cao and
                  Chia{-}Yu Chen and
                  Pierce Chuang and
                  Thomas W. Fox and
                  George Gristede and
                  Michael Guillorn and
                  Howard Haynie and
                  Michael J. Klaiber and
                  Dongsoo Lee and
                  Shih{-}Hsien Lo and
                  Gary W. Maier and
                  Michael Scheuermann and
                  Swagath Venkataramani and
                  Christos Vezyrtzis and
                  Naigang Wang and
                  Fanchieh Yee and
                  Ching Zhou and
                  Pong{-}Fei Lu and
                  Brian W. Curran and
                  Leland Chang and
                  Kailash Gopalakrishnan},
  title        = {Across the Stack Opportunities for Deep Learning Acceleration},
  booktitle    = {Proceedings of the International Symposium on Low Power Electronics
                  and Design, {ISLPED} 2018, Seattle, WA, USA, July 23-25, 2018},
  pages        = {35:1--35:2},
  publisher    = {{ACM}},
  year         = {2018},
  url          = {https://doi.org/10.1145/3218603.3241339},
  doi          = {10.1145/3218603.3241339},
  timestamp    = {Tue, 22 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/islped/SrinivasanFSZSO18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FleischerSZSOSC18,
  author       = {Bruce M. Fleischer and
                  Sunil Shukla and
                  Matthew M. Ziegler and
                  Joel Silberman and
                  Jinwook Oh and
                  Vijayalakshmi Srinivasan and
                  Jungwook Choi and
                  Silvia M. Mueller and
                  Ankur Agrawal and
                  Tina Babinsky and
                  Nianzheng Cao and
                  Chia{-}Yu Chen and
                  Pierce Chuang and
                  Thomas W. Fox and
                  George Gristede and
                  Michael Guillorn and
                  Howard Haynie and
                  Michael J. Klaiber and
                  Dongsoo Lee and
                  Shih{-}Hsien Lo and
                  Gary W. Maier and
                  Michael Scheuermann and
                  Swagath Venkataramani and
                  Christos Vezyrtzis and
                  Naigang Wang and
                  Fanchieh Yee and
                  Ching Zhou and
                  Pong{-}Fei Lu and
                  Brian W. Curran and
                  Leland Chang and
                  Kailash Gopalakrishnan},
  title        = {A Scalable Multi- TeraOPS Deep Learning Processor Core for {AI} Trainina
                  and Inference},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {35--36},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502276},
  doi          = {10.1109/VLSIC.2018.8502276},
  timestamp    = {Tue, 22 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsic/FleischerSZSOSC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/CurranJBSAPH15,
  author       = {Brian W. Curran and
                  Christian Jacobi and
                  J. J. Bonanno and
                  D. A. Schroter and
                  K. J. Alexander and
                  A. Puranik and
                  Markus M. Helms},
  title        = {The {IBM} z13 multithreaded microprocessor},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {59},
  number       = {4/5},
  year         = {2015},
  url          = {https://doi.org/10.1147/JRD.2015.2418591},
  doi          = {10.1147/JRD.2015.2418591},
  timestamp    = {Tue, 19 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ibmrd/CurranJBSAPH15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/WebelLBSARCSBLB15,
  author       = {Tobias Webel and
                  Preetham M. Lobo and
                  Ramon Bertran and
                  Gerard Salem and
                  Malcolm Allen{-}Ware and
                  Richard F. Rizzolo and
                  Sean M. Carey and
                  Thomas Strach and
                  Alper Buyuktosunoglu and
                  Charles Lefurgy and
                  Pradip Bose and
                  Ricardo Nigaglioni and
                  Timothy J. Slegel and
                  Michael S. Floyd and
                  Brian W. Curran},
  title        = {Robust power management in the {IBM} z13},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {59},
  number       = {4/5},
  year         = {2015},
  url          = {https://doi.org/10.1147/JRD.2015.2446872},
  doi          = {10.1147/JRD.2015.2446872},
  timestamp    = {Thu, 04 Mar 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/WebelLBSARCSBLB15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockCBFPCCSS15,
  author       = {James D. Warnock and
                  Brian W. Curran and
                  John Badar and
                  Gregory Fredeman and
                  Donald W. Plass and
                  Yuen H. Chan and
                  Sean M. Carey and
                  Gerard Salem and
                  Friedrich Schroeder and
                  Frank Malgioglio and
                  Guenter Mayer and
                  Christopher J. Berry and
                  Michael H. Wood and
                  Yiu{-}Hing Chan and
                  Mark D. Mayo and
                  John Isakson and
                  Charudhattan Nagarajan and
                  Tobias Werner and
                  Leon J. Sigal and
                  Ricardo Nigaglioni and
                  Mark Cichanowski and
                  Jeffrey A. Zitz and
                  Matthew M. Ziegler and
                  Tim Bronson and
                  Gerald Strevig and
                  Daniel Dreps and
                  Ruchir Puri and
                  Douglas Malone and
                  Dieter F. Wendel and
                  Pak{-}kin Mak and
                  Michael A. Blake},
  title        = {4.1 22nm Next-generation {IBM} System z microprocessor},
  booktitle    = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2015, Digest of Technical Papers, San Francisco, CA, USA, February
                  22-26, 2015},
  pages        = {1--3},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/ISSCC.2015.7062930},
  doi          = {10.1109/ISSCC.2015.7062930},
  timestamp    = {Wed, 22 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/WarnockCBFPCCSS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/BusabaBCFJMPW12,
  author       = {Fadi Busaba and
                  Michael A. Blake and
                  Brian W. Curran and
                  Michael F. Fee and
                  Christian Jacobi and
                  Pak{-}kin Mak and
                  Brian R. Prasky and
                  Craig R. Walters},
  title        = {{IBM} zEnterprise 196 microprocessor and cache subsystem},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {56},
  number       = {1},
  pages        = {1},
  year         = {2012},
  url          = {https://doi.org/10.1147/JRD.2011.2173962},
  doi          = {10.1147/JRD.2011.2173962},
  timestamp    = {Sun, 12 Feb 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/BusabaBCFJMPW12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/CurranESMWMF11,
  author       = {Brian W. Curran and
                  Lee Eisen and
                  Eric M. Schwarz and
                  Pak{-}kin Mak and
                  James D. Warnock and
                  Patrick J. Meaney and
                  Michael F. Fee},
  title        = {The zEnterprise 196 System and Microprocessor},
  journal      = {{IEEE} Micro},
  volume       = {31},
  number       = {2},
  pages        = {26--40},
  year         = {2011},
  url          = {https://doi.org/10.1109/MM.2011.34},
  doi          = {10.1109/MM.2011.34},
  timestamp    = {Sat, 20 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/micro/CurranESMWMF11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WarnockCHCFWSMMPCMMSRAWSSCSEMWMMW11,
  author       = {James D. Warnock and
                  Y. Chan and
                  William V. Huott and
                  Sean M. Carey and
                  Michael F. Fee and
                  Huajun Wen and
                  Mary Jo Saccamango and
                  Frank Malgioglio and
                  Patrick J. Meaney and
                  Donald W. Plass and
                  Yuen H. Chan and
                  Mark D. Mayo and
                  Guenter Mayer and
                  Leon J. Sigal and
                  David L. Rude and
                  Robert M. Averill III and
                  Michael H. Wood and
                  Thomas Strach and
                  Howard H. Smith and
                  Brian W. Curran and
                  Eric M. Schwarz and
                  Lee Eisen and
                  Doug Malone and
                  Steve Weitzel and
                  Pak{-}kin Mak and
                  Thomas J. McPherson and
                  Charles F. Webb},
  title        = {A 5.2GHz microprocessor chip for the {IBM} zEnterprise{\texttrademark}
                  system},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
                  Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
                  2011},
  pages        = {70--72},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISSCC.2011.5746223},
  doi          = {10.1109/ISSCC.2011.5746223},
  timestamp    = {Thu, 07 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/WarnockCHCFWSMMPCMMSRAWSSCSEMWMMW11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/Curran10,
  author       = {Brian W. Curran},
  title        = {{IBM} zEnterprise 196 processor},
  booktitle    = {2010 {IEEE} Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24,
                  2010},
  pages        = {1--31},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2010.7480085},
  doi          = {10.1109/HOTCHIPS.2010.7480085},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/hotchips/Curran10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/CurranFPSFCH07,
  author       = {Brian W. Curran and
                  Eric Fluhr and
                  Jose Paredes and
                  Leon J. Sigal and
                  Joshua Friedrich and
                  Yiu{-}Hing Chan and
                  Charlie Hwang},
  title        = {Power-constrained high-frequency circuits for the {IBM} {POWER6} microprocessor},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {51},
  number       = {6},
  pages        = {715--732},
  year         = {2007},
  url          = {https://doi.org/10.1147/rd.516.0715},
  doi          = {10.1147/RD.516.0715},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/CurranFPSFCH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FriedrichMJHCFMCCPCLCRTDL07,
  author       = {Joshua Friedrich and
                  Bradley D. McCredie and
                  Norman K. James and
                  Bill Huott and
                  Brian W. Curran and
                  Eric Fluhr and
                  Gaurav Mittal and
                  Eddie Chan and
                  Yuen H. Chan and
                  Donald W. Plass and
                  Sam G. Chu and
                  Hung Q. Le and
                  Leo Clark and
                  John R. Ripley and
                  Scott A. Taylor and
                  Jack DiLullo and
                  Mary Yvonne Lanzerotti},
  title        = {Design of the Power6 Microprocessor},
  booktitle    = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2007, Digest of Technical Papers, San Francisco, CA, USA, February
                  11-15, 2007},
  pages        = {96--97},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/ISSCC.2007.373605},
  doi          = {10.1109/ISSCC.2007.373605},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/FriedrichMJHCFMCCPCLCRTDL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/CurranMSSFCWVG06,
  author       = {Brian W. Curran and
                  Bradley D. McCredie and
                  Leonid Sigal and
                  Eric M. Schwarz and
                  Bruce M. Fleischer and
                  Yuen H. Chan and
                  D. Webber and
                  Vaden Vaden and
                  A. Goyal},
  title        = {4GHz+ low-latency fixed-point and binary floating-point execution
                  units for the {POWER6} processor},
  booktitle    = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
                  2006, Digest of Technical Papers, an Francisco, CA, USA, February
                  6-9, 2006},
  pages        = {1728--1734},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSCC.2006.1696229},
  doi          = {10.1109/ISSCC.2006.1696229},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/CurranMSSFCWVG06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/CurranCWCNHLEHS02,
  author       = {Brian W. Curran and
                  Yuen H. Chan and
                  Philip T. Wu and
                  Peter J. Camporese and
                  Gregory A. Northrop and
                  Robert F. Hatch and
                  Lisa B. Lacey and
                  James P. Eckhardt and
                  David T. Hui and
                  Howard H. Smith},
  title        = {{IBM} eServer z900 high-frequency microprocessor technology, circuits,
                  and design methodology},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {46},
  number       = {4-5},
  pages        = {631},
  year         = {2002},
  url          = {https://doi.org/10.1147/rd.464.0631},
  doi          = {10.1147/RD.464.0631},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/CurranCWCNHLEHS02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ifip10-5/CurranGMBMA01,
  author       = {Brian W. Curran and
                  Mary Gifaldi and
                  Jason Martin and
                  Alper Buyuktosunoglu and
                  Martin Margala and
                  David H. Albonesi},
  editor       = {Michel Robert and
                  Bruno Rouzeyre and
                  Christian Piguet and
                  Marie{-}Lise Flottes},
  title        = {Low-Voltage 0, 25 {\(\mathrm{\mu}\)}m {CMOS} Improved Power Adaptive
                  Issue Queue for Embedded Microprocessors},
  booktitle    = {{SOC} Design Methodologies, {IFIP} {TC10/WG10.5} Eleventh International
                  Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01),
                  December 3-5, 2001, Montpellier, France},
  series       = {{IFIP} Conference Proceedings},
  volume       = {218},
  pages        = {289--300},
  publisher    = {Kluwer},
  year         = {2001},
  timestamp    = {Tue, 13 Aug 2002 16:01:37 +0200},
  biburl       = {https://dblp.org/rec/conf/ifip10-5/CurranGMBMA01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/HoffmanACCDHMMNSPW98,
  author       = {Dale E. Hoffman and
                  Robert M. Averill III and
                  Brian W. Curran and
                  Yuen H. Chan and
                  Allan H. Dansky and
                  Robert F. Hatch and
                  Timothy G. McNamara and
                  Thomas J. McPherson and
                  Gregory A. Northrop and
                  Leon J. Sigal and
                  Anthony Pelella and
                  Patrick M. Williams},
  title        = {Deep submicron design techniques for the 500 MHz {IBM} {S/390} {G5}
                  custom microprocessor},
  booktitle    = {International Conference on Computer Design: {VLSI} in Computers and
                  Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
                  {USA}},
  pages        = {258--263},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/ICCD.1998.727059},
  doi          = {10.1109/ICCD.1998.727059},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/HoffmanACCDHMMNSPW98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/SigalWCCCMHKCEW97,
  author       = {Leon J. Sigal and
                  James D. Warnock and
                  Brian W. Curran and
                  Yuen H. Chan and
                  Peter J. Camporese and
                  Mark D. Mayo and
                  William V. Huott and
                  Daniel R. Knebel and
                  Ching{-}Te Chuang and
                  James P. Eckhardt and
                  Philip T. Wu},
  title        = {Circuit design techniques for the high-performance {CMOS} {IBM} {S/390}
                  Parallel Enterprise Server {G4} microprocessor},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {41},
  number       = {4{\&}5},
  pages        = {489--504},
  year         = {1997},
  url          = {https://doi.org/10.1147/rd.414.0489},
  doi          = {10.1147/RD.414.0489},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/SigalWCCCMHKCEW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/ShepardCCCHHMNS97,
  author       = {Kenneth L. Shepard and
                  Sean M. Carey and
                  Ee Kin Cho and
                  Brian W. Curran and
                  Robert F. Hatch and
                  Dale E. Hoffman and
                  Scott A. McCabe and
                  Gregory A. Northrop and
                  A. E. (Rick) Seigler},
  title        = {Design methodology for the {S/390} Parallel Enterprise Server {G4}
                  microprocessors},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {41},
  number       = {4{\&}5},
  pages        = {515--548},
  year         = {1997},
  url          = {https://doi.org/10.1147/rd.414.0515},
  doi          = {10.1147/RD.414.0515},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/ShepardCCCHHMNS97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WebbASSLWCKMCSF97,
  author       = {Charles F. Webb and
                  Carl J. Anderson and
                  Leon J. Sigal and
                  Kenneth L. Shepard and
                  John S. Liptay and
                  James D. Warnock and
                  Brian W. Curran and
                  Barry Krumm and
                  Mark D. Mayo and
                  Peter J. Camporese and
                  Eric M. Schwarz and
                  Mark S. Farrell and
                  Phillip J. Restle and
                  Robert M. Averill III and
                  Timothy J. Slegel and
                  William V. Huott and
                  Yuen H. Chan and
                  Bruce Wile and
                  Thao N. Nguyen and
                  Philip G. Emma and
                  Daniel K. Beece and
                  Ching{-}Te Chuang and
                  Cyril Price},
  title        = {A 4.1-ns compact 54{\texttimes}54-b multiplier utilizing sign-select
                  Booth encoders},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {32},
  number       = {11},
  pages        = {1676--1682},
  year         = {1997},
  url          = {https://doi.org/10.1109/4.641687},
  doi          = {10.1109/4.641687},
  timestamp    = {Tue, 26 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WebbASSLWCKMCSF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/WarnockSCC97,
  author       = {James D. Warnock and
                  Leon J. Sigal and
                  Brian W. Curran and
                  Yuen H. Chan},
  title        = {High-Performance {CMOS} Circuit Techniques for the {G-4} {S/390} Microprocessor},
  booktitle    = {Proceedings 1997 International Conference on Computer Design: {VLSI}
                  in Computers {\&} Processors, {ICCD} '97, Austin, Texas, USA,
                  October 12-15, 1997},
  pages        = {247--252},
  publisher    = {{IEEE} Computer Society},
  year         = {1997},
  url          = {https://doi.org/10.1109/ICCD.1997.628875},
  doi          = {10.1109/ICCD.1997.628875},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/WarnockSCC97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/ChenC96,
  author       = {C. L. Chen and
                  Brian W. Curran},
  title        = {Switching Codes for Delta-I Noise Reduction},
  journal      = {{IEEE} Trans. Computers},
  volume       = {45},
  number       = {9},
  pages        = {1017--1021},
  year         = {1996},
  url          = {https://doi.org/10.1109/12.537124},
  doi          = {10.1109/12.537124},
  timestamp    = {Sat, 20 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tc/ChenC96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/CurranW91,
  author       = {Brian W. Curran and
                  Manfred H. Walz},
  title        = {{IBM} Enterprise System/9000 Type 9121 system controller and memory
                  subsystem design},
  journal      = {{IBM} J. Res. Dev.},
  volume       = {35},
  number       = {3},
  pages        = {357--366},
  year         = {1991},
  url          = {https://doi.org/10.1147/rd.353.0357},
  doi          = {10.1147/RD.353.0357},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ibmrd/CurranW91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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