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ORCIDBibTeX records: Vivek De
@article{DBLP:journals/jssc/KumarVTTDM24,
author = {Raghavan Kumar and
Avinash L. Varna and
Carlos Tokunaga and
Sachin Taneja and
Vivek De and
Sanu K. Mathew},
title = {A 100-Gbps Fault-Injection Attack-Resistant {AES-256} Engine With
99.1{\%}-99.99{\%} Error Coverage in Intel 4 {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {1},
pages = {79--89},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3305188},
doi = {10.1109/JSSC.2023.3305188},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KumarVTTDM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimKADWADYBLRRTD24,
author = {Suhwan Kim and
Harish K. Krishnamurthy and
Zakir Ahmed and
Nachiket V. Desai and
Sheldon Weng and
Anne Augustine and
Huong T. Do and
Jingshu Yu and
Phong D. Bach and
Xiaosen Liu and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {14.9 {A} Monolithic 10.5W/mm\({}^{\mbox{2}}\)600 MHz Top-Metal and
{C4} Planar Spiral Inductor-Based Integrated Buck Voltage Regulator
on 16nm-Class {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {270--272},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454473},
doi = {10.1109/ISSCC49657.2024.10454473},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KimKADWADYBLRRTD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiWMDS24,
author = {Mao Li and
Zhaoqing Wang and
Sanu K. Mathew and
Vivek De and
Mingoo Seok},
title = {16.6 {PACTOR:} {A} Variation-Tolerant Probing-Attack Detector for
a 2.5Gb/s{\texttimes}4-Channel Chip-to-Chip Interface in 28nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {306--308},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454309},
doi = {10.1109/ISSCC49657.2024.10454309},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiWMDS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KumarSTAHADM23,
author = {Raghavan Kumar and
Vikram B. Suresh and
Sachin Taneja and
Mark A. Anders and
Steven Hsu and
Amit Agarwal and
Vivek De and
Sanu K. Mathew},
title = {A 7-Gbps SCA-Resistant Multiplicative-Masked {AES} Engine in Intel
4 {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {4},
pages = {1106--1116},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3230372},
doi = {10.1109/JSSC.2022.3230372},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KumarSTAHADM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimKSWWRRDTD23,
author = {Suhwan Kim and
Harish K. Krishnamurthy and
Sergey Sofer and
Sheldon Weng and
Shahar Wolf and
Ashoke Ravi and
Krishnan Ravichandran and
Ofir Degani and
James W. Tschanz and
Vivek De},
title = {A 1.8W High-Frequency {SIMO} Converter Featuring Digital Sensor-Less
Computational Zero-Current Operation and Non-Linear Duty-Boost},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {186--187},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067637},
doi = {10.1109/ISSCC42615.2023.10067637},
timestamp = {Wed, 29 Mar 2023 15:53:39 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimKSWWRRDTD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KumarVTTDM23,
author = {Raghavan Kumar and
Avinash Varna and
Carlos Tokunaga and
Sachin Taneja and
Vivek De and
Sanu Mathew},
title = {A 100Gbps Fault-Injection Attack Resistant {AES-256} Engine with 99.1-to-99.99{\%}
Error Coverage in Intel 4 {CMOS}},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {244--245},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067715},
doi = {10.1109/ISSCC42615.2023.10067715},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KumarVTTDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/AugustineMLVBMT23,
author = {Charles Augustine and
Pascal Meinerzhagen and
Wootaek Lim and
A. Veerabathini and
M. Bright and
K. Mojjada and
Jim Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop
Monitor Using Coupled Ring Oscillators in Intel 4 {CMOS}},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185254},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185254},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/AugustineMLVBMT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/TanejaSKDM23,
author = {Sachin Taneja and
Vikram B. Suresh and
Raghavan Kumar and
Vivek De and
Sanu Mathew},
title = {218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication
Accelerator with a Crypto-Double-Coupled {PUF} in 4nm class {CMOS}},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185214},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185214},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/TanejaSKDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/FosterOHD22,
author = {Harry Foster and
Rob Oshana and
J{\"{o}}rg Henkel and
Vivek De},
title = {Report on the Design Automation Conference {(DAC} 2021)},
journal = {{IEEE} Des. Test},
volume = {39},
number = {1},
pages = {97--99},
year = {2022},
url = {https://doi.org/10.1109/MDAT.2021.3138609},
doi = {10.1109/MDAT.2021.3138609},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/FosterOHD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/GhoshDDDGS22,
author = {Archisman Ghosh and
Debayan Das and
Josef Danial and
Vivek De and
Santosh Ghosh and
Shreyas Sen},
title = {Syn-STELLAR: An EM/Power SCA-Resilient {AES-256} With Synthesis-Friendly
Signature Attenuation},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {1},
pages = {167--181},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3113335},
doi = {10.1109/JSSC.2021.3113335},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/GhoshDDDGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DesaiTYKLBWSRRT22,
author = {Nachiket V. Desai and
Han Wui Then and
Jingshu Yu and
Harish K. Krishnamurthy and
William J. Lambert and
Nicolas Butzen and
Sheldon Weng and
Christopher Schaef and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A 32-A, 5-V-Input, 94.2{\%} Peak Efficiency High-Frequency Power Converter
Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {4},
pages = {1090--1099},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3141779},
doi = {10.1109/JSSC.2022.3141779},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DesaiTYKLBWSRRT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CraftonWSYWTDR22,
author = {Brian Crafton and
Zishen Wan and
Samuel Spetalnick and
Jong{-}Hyeok Yoon and
Wei Wu and
Carlos Tokunaga and
Vivek De and
Arijit Raychowdhury},
editor = {Rob Oshana},
title = {Improving compute in-memory {ECC} reliability with successive correction},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {745--750},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530526},
doi = {10.1145/3489517.3530526},
timestamp = {Thu, 25 Aug 2022 14:23:32 +0200},
biburl = {https://dblp.org/rec/conf/dac/CraftonWSYWTDR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/IlderemPTKD22,
author = {Vida Ilderem and
Stefano Pellerano and
Jim Tschanz and
Tanay Karnik and
Vivek De},
title = {Innovations for Intelligent Edge},
booktitle = {48th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2022,
Milan, Italy, September 19-22, 2022},
pages = {41--44},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ESSCIRC55480.2022.9911499},
doi = {10.1109/ESSCIRC55480.2022.9911499},
timestamp = {Fri, 04 Nov 2022 09:08:31 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/IlderemPTKD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/0001H0PKTD22,
author = {Amit Agarwal and
Steven Hsu and
Mark A. Anders and
Gunjan Pandya and
Ram Krishnamurthy and
James W. Tschanz and
Vivek De},
title = {On-Chip High-Resolution Timing Characterization Circuits for Memory
IPs},
booktitle = {48th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2022,
Milan, Italy, September 19-22, 2022},
pages = {377--380},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ESSCIRC55480.2022.9911374},
doi = {10.1109/ESSCIRC55480.2022.9911374},
timestamp = {Mon, 07 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/0001H0PKTD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KumarS0H0DM22,
author = {Raghavan Kumar and
Vikram B. Suresh and
Mark A. Anders and
Steven K. Hsu and
Amit Agarwal and
Vivek K. De and
Sanu K. Mathew},
title = {An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk
{AES} Engine in Intel 4 {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {1--3},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731739},
doi = {10.1109/ISSCC42614.2022.9731739},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KumarS0H0DM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuKLRADBTD22,
author = {Xiaosen Liu and
Harish Krishnamurthy and
Renzhi Liu and
Krishnan Ravichandran and
Zakir Ahmed and
Nachiket V. Desai and
Nicolas Butzen and
James W. Tschanz and
Vivek De},
title = {A 0.76V Vin Triode Region 4A Analog {LDO} with Distributed Gain Enhancement
and Dynamic Load-Current Tracking in Intel 4 {CMOS} Featuring Active
Feedforward Ripple Shaping and On-Chip Power Noise Analyzer},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {478--480},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731792},
doi = {10.1109/ISSCC42614.2022.9731792},
timestamp = {Mon, 21 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/LiuKLRADBTD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/Hsu00RSM0TD22,
author = {Steven Hsu and
Amit Agarwal and
Mark A. Anders and
Arnab Raha and
Raymond Sung and
Deepak Mathaikutty and
Ram Krishnamurthy and
James W. Tschanz and
Vivek De},
title = {2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with
Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {22--23},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830489},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830489},
timestamp = {Thu, 04 Aug 2022 10:53:40 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/Hsu00RSM0TD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/KumarST0H0DM22,
author = {Raghavan Kumar and
Vikram B. Suresh and
Sachin Taneja and
Mark A. Anders and
Steven Hsu and
Amit Agarwal and
Vivek De and
Sanu Mathew},
title = {A 7Gbps SCA-Resistant Multiplicative-Masked {AES} Engine in Intel
4 {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {138--139},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830470},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830470},
timestamp = {Thu, 04 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/KumarST0H0DM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/DesaiKKSWCLRTD22,
author = {Nachiket V. Desai and
Harish K. Krishnamurthy and
Suhwan Kim and
Christopher Schaef and
Sheldon Weng and
Beomseok Choi and
William J. Lambert and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {Fully Integrated Voltage Regulators with Package-Embedded Inductors
for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm {CMOS}
Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled
ON-Time Discontinuous Conduction Mode {(DCM)} Operation},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {192--193},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830385},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830385},
timestamp = {Thu, 04 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/DesaiKKSWCLRTD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KumarLSKSAKRDM21,
author = {Raghavan Kumar and
Xiaosen Liu and
Vikram B. Suresh and
Harish K. Krishnamurthy and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Krishnan Ravichandran and
Vivek De and
Sanu K. Mathew},
title = {A Time-/Frequency-Domain Side-Channel Attack Resistant {AES-128} and
{RSA-4K} Crypto-Processor in 14-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {4},
pages = {1141--1151},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3052146},
doi = {10.1109/JSSC.2021.3052146},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KumarLSKSAKRDM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LiuKNWASRTD21,
author = {Xiaosen Liu and
Harish K. Krishnamurthy and
Taesik Na and
Sheldon Weng and
Khondker Z. Ahmed and
Christopher Schaef and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Universal Modular Hybrid {LDO} With Fast Load Transient Response
and Programmable {PSRR} in 14-nm {CMOS} Featuring Dynamic Clamp Strength
Tuning},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {8},
pages = {2402--2415},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3055742},
doi = {10.1109/JSSC.2021.3055742},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LiuKNWASRTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/IyerDIKCHKHK21,
author = {Ravi R. Iyer and
Vivek De and
Ramesh Illikkal and
David A. Koufaty and
Bhushan Chitlur and
Andrew Herdrich and
Muhammad M. Khellah and
Fatih Hamzaoglu and
Eric Karl},
title = {Advances in Microprocessor Cache Architectures Over the Last 25 Years},
journal = {{IEEE} Micro},
volume = {41},
number = {6},
pages = {78--88},
year = {2021},
url = {https://doi.org/10.1109/MM.2021.3114903},
doi = {10.1109/MM.2021.3114903},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/IyerDIKCHKHK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VangalPHAKKKTDK21,
author = {Sriram R. Vangal and
Somnath Paul and
Steven Hsu and
Amit Agarwal and
Saurabh Kumar and
Ram Krishnamurthy and
Harish Krishnamurthy and
James W. Tschanz and
Vivek De and
Chris H. Kim},
title = {Wide-Range Many-Core SoC Design in Scaled {CMOS:} Challenges and Opportunities},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {843--856},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3061649},
doi = {10.1109/TVLSI.2021.3061649},
timestamp = {Thu, 24 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VangalPHAKKKTDK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarCEMLTKTDK21,
author = {Saurabh Kumar and
Minki Cho and
Luke R. Everson and
Andres Malavasi and
Dan Lake and
Carlos Tokunaga and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De and
Chris H. Kim},
title = {A Back-Sampling Chain Technique for Accelerated Detection, Characterization,
and Reconstruction of Radiation-Induced Transient Pulses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2086--2097},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3119462},
doi = {10.1109/TVLSI.2021.3119462},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarCEMLTKTDK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/CraftonSYWTDR21,
author = {Brian Crafton and
Samuel Spetalnick and
Jong{-}Hyeok Yoon and
Wei Wu and
Carlos Tokunaga and
Vivek De and
Arijit Raychowdhury},
title = {{CIM-SECDED:} {A} 40nm 64Kb Compute In-Memory {RRAM} Macro with {ECC}
Enabling Reliable Operation},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2021, Busan,
Korea, Republic of, November 7-10, 2021},
pages = {1--3},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/A-SSCC53895.2021.9634742},
doi = {10.1109/A-SSCC53895.2021.9634742},
timestamp = {Tue, 21 Dec 2021 17:54:16 +0100},
biburl = {https://dblp.org/rec/conf/asscc/CraftonSYWTDR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DesaiKAWKLDRRTD21,
author = {Nachiket V. Desai and
Harish K. Krishnamurthy and
Khondker Zakir Ahmed and
Sheldon Weng and
Suhwan Kim and
Xiaosen Liu and
Huong Do and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage
Regulators in 22nm {CMOS} for Robust Cross-Tile Current Sharing},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {262--264},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365957},
doi = {10.1109/ISSCC42613.2021.9365957},
timestamp = {Wed, 10 Mar 2021 15:02:58 +0100},
biburl = {https://dblp.org/rec/conf/isscc/DesaiKAWKLDRRTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GhoshDDDGS21,
author = {Archisman Ghosh and
Debayan Das and
Josef Danial and
Vivek De and
Santosh Ghosh and
Shreyas Sen},
title = {36.2 An EM/Power SCA-Resilient {AES-256} with Synthesizable Signature
Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based
Integrated Local Feedback and Global Switched-Mode Control},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {499--501},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365978},
doi = {10.1109/ISSCC42613.2021.9365978},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GhoshDDDGS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AhmedDKWLRTD21,
author = {Khondker Zakir Ahmed and
Nachiket V. Desai and
Harish K. Krishnamurthy and
Sheldon Weng and
Xiaosen Liu and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient
Response, Zero-Wire Current Handover {\&} Input {PDN} Resonance
Reduction},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492446},
doi = {10.23919/VLSICIRCUITS52068.2021.9492446},
timestamp = {Mon, 02 Aug 2021 16:52:31 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AhmedDKWLRTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DesaiKLYTBWSNRR21,
author = {Nachiket V. Desai and
Harish K. Krishnamurthy and
William J. Lambert and
Jingshu Yu and
Han Wui Then and
Nicolas Butzen and
Sheldon Weng and
Christopher Schaef and
N. Nidhi and
Marko Radosavljevic and
Johann Rode and
Justin Sandford and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
Bernhard Sell and
James W. Tschanz and
Vivek De},
title = {A 32A 5V-Input, 94.2{\%} Peak Efficiency High-Frequency Power Converter
Module Featuring Package-Integrated Low-Voltage GaN {NMOS} Power Transistors},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492350},
doi = {10.23919/VLSICIRCUITS52068.2021.9492350},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/DesaiKLYTBWSNRR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimKAWFDRRTD21,
author = {Suhwan Kim and
Harish Krishnamurthy and
Sally Amin and
Sheldon Weng and
Jin Feng and
Huong Do and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with
5-Stack Thin-Gate 22nm FinFET {CMOS} Featuring Active Voltage Balancing
and Cascaded Self-Turn-ON Drivers},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492516},
doi = {10.23919/VLSICIRCUITS52068.2021.9492516},
timestamp = {Mon, 02 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KimKAWFDRRTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinghKCMRDM20,
author = {Arvind Singh and
Monodeep Kar and
Venkata Chaitanya Krishna Chekuri and
Sanu K. Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Enhanced Power and Electromagnetic {SCA} Resistance of Encryption
Engines via a Security-Aware Integrated All-Digital {LDO}},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {2},
pages = {478--493},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2945944},
doi = {10.1109/JSSC.2019.2945944},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinghKCMRDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KumarSKSAKAHCKD20,
author = {Raghavan Kumar and
Vikram B. Suresh and
Monodeep Kar and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram K. Krishnamurthy and
Vivek De and
Sanu K. Mathew},
title = {A 4900- {\textdollar}{\textbackslash}mu{\textdollar} m\({}^{\mbox{2}}\)
839-Mb/s Side-Channel Attack- Resistant {AES-128} in 14-nm {CMOS}
With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail
Key Addition},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {4},
pages = {945--955},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2960482},
doi = {10.1109/JSSC.2019.2960482},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KumarSKSAKAHCKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AhmedKALWRTD20,
author = {Khondker Zakir Ahmed and
Harish K. Krishnamurthy and
Charles Augustine and
Xiaosen Liu and
Sheldon Weng and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Variation-Adaptive Integrated Computational Digital {LDO} in 22-nm
{CMOS} With Fast Transient Response},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {4},
pages = {977--987},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2961854},
doi = {10.1109/JSSC.2019.2961854},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AhmedKALWRTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BangCMMKTD20,
author = {Suyoung Bang and
Minki Cho and
Pascal Andreas Meinerzhagen and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An All-Digital, {\textdollar}V{\_}\{{\textbackslash}mathrm\{MAX\}\}{\textdollar}
-Compliant, Stable, and Scalable Distributed Charge Injection Scheme
in 10-nm {CMOS} for Fast and Local Mitigation of Voltage Droop},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {7},
pages = {1898--1908},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2020.2992892},
doi = {10.1109/JSSC.2020.2992892},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BangCMMKTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KrishnamurthyAL20,
author = {Harish K. Krishnamurthy and
Khondker Zakir Ahmed and
Xiaosen Liu and
Nachiket V. Desai and
Suhwan Kim and
Nicolas Butzen and
Sally Amin and
Sheldon Weng and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {Digital Control of Switching and Linear Integrated Voltage Regulators},
booktitle = {2020 {IEEE} Custom Integrated Circuits Conference, {CICC} 2020, Boston,
MA, USA, March 22-25, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CICC48029.2020.9075934},
doi = {10.1109/CICC48029.2020.9075934},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KrishnamurthyAL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BangLAMKTD20,
author = {Suyoung Bang and
Wootaek Lim and
Charles Augustine and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {25.1 {A} Fully Synthesizable Distributed and Scalable All-Digital
{LDO} in 10nm {CMOS}},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {380--382},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063040},
doi = {10.1109/ISSCC19947.2020.9063040},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BangLAMKTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/0001HRACKKSKKMK20,
author = {Amit Agarwal and
Steven Hsu and
Simeon Realov and
Mark A. Anders and
Gregory K. Chen and
Monodeep Kar and
Raghavan Kumar and
Huseyin Sumbul and
Phil C. Knag and
Himanshu Kaul and
Sanu Mathew and
Mahesh Kumashikar and
Ram Krishnamurthy and
Vivek De},
title = {25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN
Characterization Circuits in 10nm {CMOS}},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {392--394},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062941},
doi = {10.1109/ISSCC19947.2020.9062941},
timestamp = {Thu, 03 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/0001HRACKKSKKMK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AndersKKCKSKKH020,
author = {Mark A. Anders and
Himanshu Kaul and
Seongjong Kim and
Gregory K. Chen and
Raghavan Kumar and
Huseyin Ekin Sumbul and
Phil C. Knag and
Monodeep Kar and
Steven K. Hsu and
Amit Agarwal and
Vikram B. Suresh and
Sanu K. Mathew and
Ram K. Krishnamurthy and
Vivek De},
title = {25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits
in 10nm {CMOS} for High-Performance Processors with Wide Voltage-Frequency
Operating Range},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {396--398},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063158},
doi = {10.1109/ISSCC19947.2020.9063158},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/AndersKKCKSKKH020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AhmedKWLSDRTD20,
author = {Zakir Zakir Ahmed and
Harish K. Krishnamurthy and
Sheldon Weng and
Xiaosen Liu and
Christopher Schaef and
Nachiket V. Desai and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {An Autonomous Reconfigurable Power Delivery Network {(RPDN)} for Many-Core
SoCs Featuring Dynamic Current Steering},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162827},
doi = {10.1109/VLSICIRCUITS18222.2020.9162827},
timestamp = {Mon, 24 Aug 2020 16:22:01 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AhmedKWLSDRTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AugustinePMTKD20,
author = {Charles Augustine and
Somnath Paul and
Turbo Majumder and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162815},
doi = {10.1109/VLSICIRCUITS18222.2020.9162815},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AugustinePMTKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Hsu0RACKKSKKSMR20,
author = {Steven Hsu and
Amit Agarwal and
Simeon Realov and
Mark A. Anders and
Gregory K. Chen and
Monodeep Kar and
Raghavan Kumar and
Huseyin Sumbul and
Phil C. Knag and
Himanshu Kaul and
Vikram B. Suresh and
Sanu Mathew and
Iqbal Rajwani and
Satish Damaraju and
Ram Krishnamurthy and
Vivek De},
title = {Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI
Processors in 10nm {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9163007},
doi = {10.1109/VLSICIRCUITS18222.2020.9163007},
timestamp = {Sun, 03 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Hsu0RACKKSKKSMR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Kar0HMCKSKAKBSK20,
author = {Monodeep Kar and
Amit Agarwal and
Steven Hsu and
David Moloney and
Gregory K. Chen and
Raghavan Kumar and
Huseyin Sumbul and
Phil C. Knag and
Mark A. Anders and
Himanshu Kaul and
Jonathan Byrne and
Luca Sarti and
Ram Krishnamurthy and
Vivek De},
title = {A Ray-Casting Accelerator in 10nm {CMOS} for Efficient 3D Scene Reconstruction
in Edge Robotics and Augmented Reality Applications},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9163067},
doi = {10.1109/VLSICIRCUITS18222.2020.9163067},
timestamp = {Sun, 03 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Kar0HMCKSKAKBSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KulkarniMATTKD20,
author = {Jaydeep P. Kulkarni and
Andres Malavasi and
Charles Augustine and
Carlos Tokunaga and
Jim Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin,
Noise-Tolerant, High-Density, 1R1W 8T-Bitcell {SRAM} in 10nm FinFET
{CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162822},
doi = {10.1109/VLSICIRCUITS18222.2020.9162822},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KulkarniMATTKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarLSKAKRDM20,
author = {Raghavan Kumar and
Xiaosen Liu and
Vikram B. Suresh and
Harish Krishnamurthy and
Mark A. Anders and
Himanshu Kaul and
Krishnan Ravichandran and
Vivek De and
Sanu Mathew},
title = {A SCA-Resistant {AES} Engine in 14nm {CMOS} with Time/Frequency-Domain
Leakage Suppression using Non-Linear Digital {LDO} Cascaded with Arithmetic
Countermeasures},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162988},
doi = {10.1109/VLSICIRCUITS18222.2020.9162988},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarLSKAKRDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarSSAKDM20,
author = {Raghavan Kumar and
Sudhir Satpathy and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Vivek De and
Sanu Mathew},
title = {A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor
for Secure {RSA-4K} Public-Key Encryption in 14nm {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162905},
doi = {10.1109/VLSICIRCUITS18222.2020.9162905},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarSSAKDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiuKBHBCARTD20,
author = {Xiaosen Liu and
Harish K. Krishnamurthy and
Claudia P. Barrera and
Jing Han and
Rajasekhara M. Narayana Bhatla and
Scott Chiu and
Khondker Zakir Ahmed and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Dual-Rail Hybrid Analog/Digital {LDO} with Dynamic Current Steering
for Tunable High {PSRR} and High Efficiency},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162880},
doi = {10.1109/VLSICIRCUITS18222.2020.9162880},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LiuKBHBCARTD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PaulMAMUKKCYBOL20,
author = {Somnath Paul and
Turbo Majumder and
Charles Augustine and
Andres F. Malavasi and
S. Usirikayala and
Raghavan Kumar and
Jisna Kollikunnel and
S. Chhabra and
Satish Yada and
M. L. Barajas and
Carlos Ornelas and
Dan Lake and
Muhammad M. Khellah and
Jim Tschanz and
Vivek De},
title = {A 0.05pJ/Pixel 70fps {FHD} 1Meps Event-Driven Visual Data Processing
Unit},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162948},
doi = {10.1109/VLSICIRCUITS18222.2020.9162948},
timestamp = {Mon, 08 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/PaulMAMUKKCYBOL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SureshKAKDM20,
author = {Vikram B. Suresh and
Raghavan Kumar and
Mark A. Anders and
Himanshu Kaul and
Vivek De and
Sanu Mathew},
title = {A 0.26{\%} BER, 10\({}^{\mbox{28}}\) Challenge-Response Machine-Learning
Resistant Strong-PUF in 14nm {CMOS} Featuring Stability-Aware Adversarial
Challenge Selection},
booktitle = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
HI, USA, June 16-19, 2020},
pages = {1--2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VLSICircuits18222.2020.9162890},
doi = {10.1109/VLSICIRCUITS18222.2020.9162890},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SureshKAKDM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ChenDHN19,
author = {An Chen and
Vivek De and
Xiaobo Sharon Hu and
Michael T. Niemier},
title = {Guest Editors' Introduction: Special Issue on Architecture Advances
Enabled by Emerging Technologies},
journal = {{IEEE} Des. Test},
volume = {36},
number = {3},
pages = {5--6},
year = {2019},
url = {https://doi.org/10.1109/MDAT.2019.2900315},
doi = {10.1109/MDAT.2019.2900315},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/ChenDHN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MeinerzhagenTMV19,
author = {Pascal Andreas Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Xiang Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An Energy-Efficient Graphics Processor in 14-nm Tri-Gate {CMOS} Featuring
Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep,
and {\textdollar}\{V\}{\_}\{{\textbackslash}text\{MIN\}\}{\textdollar}
Optimization},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {1},
pages = {144--157},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2875097},
doi = {10.1109/JSSC.2018.2875097},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MeinerzhagenTMV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinghKMRDM19,
author = {Arvind Singh and
Monodeep Kar and
Sanu K. Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Improved Power/EM Side-Channel Attack Resistance of 128-Bit {AES}
Engines With Random Fast Voltage Dithering},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {2},
pages = {569--583},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2875112},
doi = {10.1109/JSSC.2018.2875112},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinghKMRDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SatpathyMKSAKAH19,
author = {Sudhir Satpathy and
Sanu K. Mathew and
Raghavan Kumar and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram K. Krishnamurthy and
Vivek De},
title = {An All-Digital Unified Physically Unclonable Function and True Random
Number Generator Featuring Self-Calibrating Hierarchical Von Neumann
Extraction in 14-nm Tri-gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {4},
pages = {1074--1085},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2018.2886350},
doi = {10.1109/JSSC.2018.2886350},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SatpathyMKSAKAH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SchaefRRTDDKLAK19,
author = {Christopher Schaef and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De and
Nachiket V. Desai and
Harish K. Krishnamurthy and
Xiaosen Liu and
Khondker Zakir Ahmed and
Suhwan Kim and
Sheldon Weng and
Huong Do and
William J. Lambert},
title = {A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm
{CMOS} With 2.5-nH Package-Embedded Air-Core Inductors},
journal = {{IEEE} J. Solid State Circuits},
volume = {54},
number = {12},
pages = {3316--3325},
year = {2019},
url = {https://doi.org/10.1109/JSSC.2019.2946218},
doi = {10.1109/JSSC.2019.2946218},
timestamp = {Sun, 05 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SchaefRRTDDKLAK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/0001HKAKKSMKD19,
author = {Amit Agarwal and
Steven Hsu and
Monodeep Kar and
Mark A. Anders and
Himanshu Kaul and
Raghavan Kumar and
Vikram B. Suresh and
Sanu Mathew and
Ram Krishnamurthy and
Vivek De},
title = {A 54{\%} Power-Saving Static Fully-Interruptible Single-Phase-Clocked
Shared-Keeper Flip-Flop in 14nm {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {137--140},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056939},
doi = {10.1109/A-SSCC47793.2019.9056939},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/0001HKAKKSMKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/BangCMMKTD19,
author = {Suyoung Bang and
Minki Cho and
Pascal Meinerzhagen and
Andres Malavasi and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection
Scheme for Fast Mitigation of Voltage Droop},
booktitle = {45th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2019,
Cracow, Poland, September 23-26, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ESSCIRC.2019.8902534},
doi = {10.1109/ESSCIRC.2019.8902534},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/BangCMMKTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/MeinerzhagenKMN19,
author = {Pascal Andreas Meinerzhagen and
Sandip Kundu and
Andres Malavasi and
Trang Nguyen and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Min-Delay Margin/Error Detection and Correction for Flip-Flops and
Pulsed Latches in 10-nm {CMOS}},
booktitle = {45th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2019,
Cracow, Poland, September 23-26, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ESSCIRC.2019.8902924},
doi = {10.1109/ESSCIRC.2019.8902924},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/MeinerzhagenKMN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HonkoteKMGYJJKN19,
author = {Vinayak Honkote and
Dileep Kurian and
Sriram Muthukumar and
Dibyendu Ghosh and
Satish Yada and
Kartik Jain and
Bradley Jackson and
Ilya Klotchkov and
Mallikarjuna Rao Nimmagadda and
Shreela Dattawadkar and
Pranjali Deshmukh and
Ankit Gupta and
Jaykant Timbadiya and
Ravi Pali and
Karthik Narayanan and
Saksham Soni and
Saransh Chhabra and
Praveen Dhama and
N. Sreenivasulu and
Jisna Kollikunnel and
Sureshbabu Kadavakollu and
Vijay Deepak Sivaraj and
Paolo A. Aseron and
Leonid Azarenkov and
Nancy Robinson and
Arun Radhakrishnan and
Mikhail J. Moiseev and
Ganeshram Nandakumar and
Akhila Madhukumar and
Roman Popov and
Kamakhya P. Sahu and
Ramesh Peguvandla and
Alberto Del Rio Ruiz and
Mukesh Bhartiya and
Anuradha Srinivasan and
Vivek De},
title = {A Distributed Autonomous and Collaborative Multi-Robot System Featuring
a Low-Power Robot SoC in 22nm {CMOS} for Integrated Battery-Powered
Minibots},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {48--50},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662463},
doi = {10.1109/ISSCC.2019.8662463},
timestamp = {Fri, 27 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HonkoteKMGYJJKN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SchaefWCLRRTD19,
author = {Christopher Schaef and
Sheldon Weng and
Beomseok Choi and
William J. Lambert and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A 93.8{\%} Peak Efficiency, 5V-Input, 10A Max {ILOAD} Flying Capacitor
Multilevel Converter in 22nm {CMOS} Featuring Wide Output Voltage
Range and Flying Capacitor Precharging},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {146--148},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662475},
doi = {10.1109/ISSCC.2019.8662475},
timestamp = {Sun, 05 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SchaefWCLRRTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SchaefDKWDLRRTD19,
author = {Christopher Schaef and
Nachiket V. Desai and
Harish Krishnamurthy and
Sheldon Weng and
Huong Do and
William J. Lambert and
Kaladhar Radhakrishnan and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Fully Integrated Voltage Regulator in 14nm {CMOS} with Package-Embedded
Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable
On-Time Discontinuous Conduction Mode Operation},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {154--156},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662294},
doi = {10.1109/ISSCC.2019.8662294},
timestamp = {Sun, 05 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SchaefDKWDLRRTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuKNWARTD19,
author = {Xiaosen Liu and
Harish K. Krishnamurthy and
Taesik Na and
Sheldon Weng and
Khondker Z. Ahmed and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Modular Hybrid {LDO} with Fast Load-Transient Response and Programmable
{PSRR} in 14nm {CMOS} Featuring Dynamic Clamp Tuning and Time-Constant
Compensation},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {234--236},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662343},
doi = {10.1109/ISSCC.2019.8662343},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiuKNWARTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SinghKMRDM19,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {A 128b {AES} Engine with Higher Resistance to Power and Electromagnetic
Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital
Low-Dropout Regulator},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {404--406},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662344},
doi = {10.1109/ISSCC.2019.8662344},
timestamp = {Tue, 12 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SinghKMRDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SureshSKAK0HKDM19,
author = {Vikram B. Suresh and
Sudhir Satpathy and
Raghavan Kumar and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm {CMOS} Featuring
Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {32},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777966},
doi = {10.23919/VLSIC.2019.8777966},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SureshSKAK0HKDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Hsu0KAKKSSMKD19,
author = {Steven Hsu and
Amit Agarwal and
Monodeep Kar and
Mark A. Anders and
Himanshu Kaul and
Raghavan Kumar and
Sudhir Satpathy and
Vikram B. Suresh and
Sanu Mathew and
Ram Krishnamurthy and
Vivek De},
title = {A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power
{AOI} Clocked Circuits in 14nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {50},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777978},
doi = {10.23919/VLSIC.2019.8777978},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Hsu0KAKKSSMKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AhmedKALWRTD19,
author = {Khondker Zakir Ahmed and
Harish K. Krishnamurthy and
Charles Augustine and
Xiaosen Liu and
Sheldon Weng and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Variation-Adaptive Integrated Computational Digital {LDO} in 22nm
{CMOS} with Fast Transient Response},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {124},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778070},
doi = {10.23919/VLSIC.2019.8778070},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AhmedKALWRTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarSKSAKAHCKD19,
author = {Raghavan Kumar and
Vikram B. Suresh and
Monodeep Kar and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 4900{\texttimes}m\({}^{\mbox{2}}\) 839Mbps Side-Channel Attack Resistant
{AES-128} in 14nm {CMOS} with Heterogeneous Sboxes, Linear Masked
MixColumns and Dual-Rail Key Addition},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {234},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778041},
doi = {10.23919/VLSIC.2019.8778041},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarSKSAKAHCKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathySKGGAKA19,
author = {Sudhir Satpathy and
Vikram B. Suresh and
Raghavan Kumar and
Vinodh Gopal and
James Guilford and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 1.4GHz 20.5Gbps {GZIP} decompression accelerator in 14nm {CMOS}
featuring dual-path out-of-order speculative Huffman decoder and multi-write
enabled register file array},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {238},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777934},
doi = {10.23919/VLSIC.2019.8777934},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathySKGGAKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/AliotoDM18,
author = {Massimo Alioto and
Vivek De and
Andrea Marongiu},
title = {Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing
and Computing: From Approximate to Communication-Inspired and Learning-Based},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {8},
number = {3},
pages = {361--368},
year = {2018},
url = {https://doi.org/10.1109/JETCAS.2018.2865783},
doi = {10.1109/JETCAS.2018.2865783},
timestamp = {Wed, 03 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/AliotoDM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/AliotoDM18a,
author = {Massimo Alioto and
Vivek De and
Andrea Marongiu},
title = {Energy-Quality Scalable Integrated Circuits and Systems: Continuing
Energy Scaling in the Twilight of Moore's Law},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {8},
number = {4},
pages = {653--678},
year = {2018},
url = {https://doi.org/10.1109/JETCAS.2018.2881461},
doi = {10.1109/JETCAS.2018.2881461},
timestamp = {Fri, 18 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/AliotoDM18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KrishnamurthyVK18,
author = {Harish Kumar Krishnamurthy and
Vaibhav A. Vaidya and
Pavan Kumar and
Rinkle Jain and
Sheldon Weng and
Stephen T. Kim and
George E. Matthew and
Nachiket V. Desai and
Xiaosen Liu and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Digitally Controlled Fully Integrated Voltage Regulator With On-Die
Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {8--19},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2759117},
doi = {10.1109/JSSC.2017.2759117},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KrishnamurthyVK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KrishnamurthyWM18,
author = {Harish Kumar Krishnamurthy and
Sheldon Weng and
George E. Matthew and
Nachiket V. Desai and
Ruchir Saraswat and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based
On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked
Die Applications in 14-nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {4},
pages = {1038--1048},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2773637},
doi = {10.1109/JSSC.2017.2773637},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KrishnamurthyWM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KarSMRDM18,
author = {Monodeep Kar and
Arvind Singh and
Sanu K. Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Reducing Power Side-Channel Information Leakage of {AES} Engines Using
Fully Integrated Inductive Voltage Regulator},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {8},
pages = {2399--2414},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2018.2822691},
doi = {10.1109/JSSC.2018.2822691},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KarSMRDM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SinghKMRDM18,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
editor = {Jan Madsen and
Ayse K. Coskun},
title = {Exploiting on-chip power management for side-channel security},
booktitle = {2018 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2018, Dresden, Germany, March 19-23, 2018},
pages = {401--406},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/DATE.2018.8342043},
doi = {10.23919/DATE.2018.8342043},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SinghKMRDM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MeinerzhagenTMV18,
author = {Pascal Meinerzhagen and
Carlos Tokunaga and
Andres Malavasi and
Vaibhav A. Vaidya and
Ashwin Mendon and
Deepak Mathaikutty and
Jaydeep Kulkarni and
Charles Augustine and
Minki Cho and
Stephen T. Kim and
George E. Matthew and
Rinkle Jain and
Joseph F. Ryan and
Chung{-}Ching Peng and
Somnath Paul and
Sriram R. Vangal and
Brando Perez Esparza and
Luis Cuellar and
Michael Woodman and
Bala Iyer and
Subramaniam Maiyuran and
Gautham N. Chinya and
Chris Zou and
Yuyun Liao and
Krishnan Ravichandran and
Hong Wang and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {An energy-efficient graphics processor featuring fine-grain {DVFS}
with integrated voltage regulators, execution-unit turbo, and retentive
sleep in 14nm tri-gate {CMOS}},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {38--40},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310172},
doi = {10.1109/ISSCC.2018.8310172},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MeinerzhagenTMV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KarnikKADANPAMZ18,
author = {Tanay Karnik and
Dileep Kurian and
Paolo A. Aseron and
Richard Dorrance and
Erkan Alpman and
Angela Nicoara and
Roman Popov and
Leonid Azarenkov and
Mikhail J. Moiseev and
Li Zhao and
Santosh Ghosh and
Rafael Misoczki and
Ankit Gupta and
M. Akhila and
Sriram Muthukumar and
Saurabh Bhandari and
Satish Yada and
Kartik Jain and
Robert Flory and
Chanitnan Kanthapanit and
Eduardo Quijano and
Bradley Jackson and
Hao Luo and
Suhwan Kim and
Vaibhav A. Vaidya and
Adel Elsherbini and
Renzhi Liu and
Farhana Sheikh and
Omesh Tickoo and
Ilya Klotchkov and
Manoj R. Sastry and
Sheldon Sun and
Mukesh Bhartiya and
Anuradha Srinivasan and
Yatin Hoskote and
Hong Wang and
Vivek De},
title = {A cm-scale self-powered intelligent and secure IoT edge mote featuring
an ultra-low-power SoC in 14nm tri-gate {CMOS}},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {46--48},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310176},
doi = {10.1109/ISSCC.2018.8310176},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/KarnikKADANPAMZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DeSMDSV18,
author = {Vivek De and
Dennis Sylvester and
James Myers and
Jun Deguchi and
Shinichiro Shiratake and
Ingrid Verbauwhede},
title = {{F1:} Intelligent energy-efficient systems at the edge of IoT},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {502--504},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310403},
doi = {10.1109/ISSCC.2018.8310403},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DeSMDSV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RestleDDF18,
author = {Phillip J. Restle and
Kostas Doris and
Vivek De and
Paul Ferguson},
title = {{EE5:} Lessons learned - Great circuits that didn't work - (Oops,
if only i had known!)},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {529--531},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310413},
doi = {10.1109/ISSCC.2018.8310413},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/RestleDDF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/De18,
author = {Vivek De},
editor = {Zhonghai Lu and
Sriram R. Vangal and
Jiang Xu and
Paul Bogdan},
title = {Keynote Talk: Many-Core SoC in Nanoscale {CMOS:} Challenges {\&}
Opportunities},
booktitle = {Twelfth {IEEE/ACM} International Symposium on Networks-on-Chip, {NOCS}
2018, Torino, Italy, October 4-5, 2018},
pages = {1},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/NOCS.2018.8512151},
doi = {10.1109/NOCS.2018.8512151},
timestamp = {Wed, 05 May 2021 09:09:43 +0200},
biburl = {https://dblp.org/rec/conf/nocs/De18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathyMSAKAHK18,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De},
title = {An All-Digital Unified Static/Dynamic Entropy Generator Featuring
Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving
Mutual Authentication in IoT Mote Platforms},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {169--170},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502369},
doi = {10.1109/VLSIC.2018.8502369},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathyMSAKAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimVSLKWLKKRTD18,
author = {Suhwan Kim and
Vaibhav A. Vaidya and
Christopher Schaef and
Andrew Lines and
Harish Krishnamurthy and
Sheldon Weng and
Xiaosen Liu and
Dileep Kurian and
Tanay Karnik and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy
Harvesting Power Management {IC} for 100{\(\mathrm{\mu}\)}W-120MW
Battery-Powered IoT Edge Nodes},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {195--196},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502301},
doi = {10.1109/VLSIC.2018.8502301},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KimVSLKWLKKRTD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1802-09096,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Santosh Ghosh and
Anand Rajan and
Vivek De and
Raheem A. Beyah and
Saibal Mukhopadhyay},
title = {Blindsight: Blinding {EM} Side-Channel Leakage using Built-In Fully
Integrated Inductive Voltage Regulator},
journal = {CoRR},
volume = {abs/1802.09096},
year = {2018},
url = {http://arxiv.org/abs/1802.09096},
eprinttype = {arXiv},
eprint = {1802.09096},
timestamp = {Fri, 12 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1802-09096.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/DeVK17,
author = {Vivek De and
Sriram R. Vangal and
Ram Krishnamurthy},
title = {Near Threshold Voltage {(NTV)} Computing: Computing in the Dark Silicon
Era},
journal = {{IEEE} Des. Test},
volume = {34},
number = {2},
pages = {24--30},
year = {2017},
url = {https://doi.org/10.1109/MDAT.2016.2573593},
doi = {10.1109/MDAT.2016.2573593},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/DeVK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jhss/SinghKMRDM17,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Reducing Side-Channel Leakage of Encryption Engines Using Integrated
Low-Dropout Voltage Regulators},
journal = {J. Hardw. Syst. Secur.},
volume = {1},
number = {4},
pages = {340--355},
year = {2017},
url = {https://doi.org/10.1007/s41635-017-0023-0},
doi = {10.1007/S41635-017-0023-0},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jhss/SinghKMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChoKTAKRTKD17,
author = {Minki Cho and
Stephen T. Kim and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution
Core Using Adaptive Voltage Scaling and Dynamic Power Gating},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {50--63},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2601319},
doi = {10.1109/JSSC.2016.2601319},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChoKTAKRTKD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SatpathyMSAKAHC17,
author = {Sudhir Satpathy and
Sanu K. Mathew and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram K. Krishnamurthy and
Vivek K. De},
title = {A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With
Selective Bit Destabilization in 14-nm Trigate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {4},
pages = {940--949},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2636859},
doi = {10.1109/JSSC.2016.2636859},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SatpathyMSAKAHC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/PaulHKMAGSMWVTD17,
author = {Somnath Paul and
Vinayak Honkote and
Ryan Gary Kim and
Turbo Majumder and
Paolo A. Aseron and
Vaughn Grossnickle and
Robert Sankman and
Debendra Mallik and
Tao Wang and
Sriram R. Vangal and
James W. Tschanz and
Vivek De},
title = {A Sub-cm\({}^{\mbox{3}}\) Energy-Harvesting Stacked Wireless Sensor
Node Featuring a Near-Threshold Voltage {IA-32} Microcontroller in
14-nm Tri-Gate {CMOS} for Always-ON Always-Sensing Applications},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {4},
pages = {961--971},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2638465},
doi = {10.1109/JSSC.2016.2638465},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/PaulHKMAGSMWVTD17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KarSRDM17,
author = {Monodeep Kar and
Arvind Singh and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {An All-Digital Fully Integrated Inductive Buck Regulator With {A}
250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in
130-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {7},
pages = {1825--1835},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2693243},
doi = {10.1109/JSSC.2017.2693243},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KarSRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SinghKMRDM17,
author = {Arvind Singh and
Monodeep Kar and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Improved power side channel attack resistance of a 128-bit {AES} engine
with random fast voltage dithering},
booktitle = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
Leuven, Belgium, September 11-14, 2017},
pages = {51--54},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ESSCIRC.2017.8094523},
doi = {10.1109/ESSCIRC.2017.8094523},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/SinghKMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/MuthukaruppanMK17,
author = {Ramnarayanan Muthukaruppan and
Tarun Mahajan and
Harish Kumar Krishnamurthy and
Sumedha Mangal and
Am Dhanashekar and
Rupak Ghayal and
Vivek De},
title = {A digitally controlled linear regulator for per-core wide-range {DVFS}
of atom{\texttrademark} cores in 14nm tri-gate {CMOS} featuring non-linear
control, adaptive gain and code roaming},
booktitle = {43rd {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2017,
Leuven, Belgium, September 11-14, 2017},
pages = {275--278},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ESSCIRC.2017.8094579},
doi = {10.1109/ESSCIRC.2017.8094579},
timestamp = {Wed, 15 Nov 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/MuthukaruppanMK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KarSMRDM17,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Invited paper: Low power requirements and side-channel protection
of encryption engines: Challenges and opportunities},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--2},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009186},
doi = {10.1109/ISLPED.2017.8009186},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/KarSMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KarSMRDM17,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {8.1 Improved power-side-channel-attack resistance of an {AES-128}
core via a security-aware integrated buck voltage regulator},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {142--143},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870301},
doi = {10.1109/ISSCC.2017.7870301},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KarSMRDM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KrishnamurthyVW17,
author = {Harish Kumar Krishnamurthy and
Vaibhav A. Vaidya and
Sheldon Weng and
Krishnan Ravichandran and
Pavan Kumar and
Stephen T. Kim and
Rinkle Jain and
George E. Matthew and
Jim Tschanz and
Vivek De},
title = {20.1 {A} digitally controlled fully integrated voltage regulator with
on-die solenoid inductor with planar magnetic core in 14nm tri-gate
{CMOS}},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {336--337},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870398},
doi = {10.1109/ISSCC.2017.7870398},
timestamp = {Wed, 05 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KrishnamurthyVW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangDDMSV17,
author = {Meng{-}Fan Chang and
Jun Deguchi and
Vivek De and
Masato Motomura and
Shinichiro Shiratake and
Marian Verhelst},
title = {{F3:} Beyond the horizon of conventional computing: From deep learning
to neuromorphic systems},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {506--508},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870481},
doi = {10.1109/ISSCC.2017.7870481},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChangDDMSV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/De16,
author = {Vivek De},
title = {Energy-Efficient Computing in Nanoscale {CMOS}},
journal = {{IEEE} Des. Test},
volume = {33},
number = {2},
pages = {68--75},
year = {2016},
url = {https://doi.org/10.1109/MDAT.2015.2513400},
doi = {10.1109/MDAT.2015.2513400},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/De16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimSMJ0TAKRTKD16,
author = {Stephen T. Kim and
Yi{-}Chun Shih and
Kaushik Mazumdar and
Rinkle Jain and
Joseph F. Ryan and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Enabling Wide Autonomous {DVFS} in a 22 nm Graphics Execution Core
Using a Digitally Controlled Fully Integrated Voltage Regulator},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {18--30},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2457920},
doi = {10.1109/JSSC.2015.2457920},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimSMJ0TAKRTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KulkarniTANATD16,
author = {Jaydeep P. Kulkarni and
Carlos Tokunaga and
Paolo A. Aseron and
Trang Nguyen and
Charles Augustine and
James W. Tschanz and
Vivek De},
title = {A 409 {GOPS/W} Adaptive and Resilient Domino Register File in 22 nm
Tri-Gate {CMOS} Featuring In-Situ Timing Margin and Error Detection
for Tolerance to Within-Die Variation, Voltage Droop, Temperature
and Aging},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {1},
pages = {117--129},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2015.2463083},
doi = {10.1109/JSSC.2015.2463083},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KulkarniTANATD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/SatpathyMSACKAH16,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Mark A. Anders and
Gregory K. Chen and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De},
title = {A 305mV-850mV 400{\(\mu\)}W 45GSamples/J reconfigurable compressive
sensing engine with early-termination for ultra-low energy target
detection in 14nm tri-gate {CMOS}},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
Japan, November 7-9, 2016},
pages = {253--256},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASSCC.2016.7844183},
doi = {10.1109/ASSCC.2016.7844183},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asscc/SatpathyMSACKAH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/KarSRDM16,
author = {Monodeep Kar and
Arvind Singh and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {An integrated inductive {VR} with a 250MHz all-digital multisampled
compensator and on-chip auto-tuning of coefficients in 130nm {CMOS}},
booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
pages = {453--456},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ESSCIRC.2016.7598339},
doi = {10.1109/ESSCIRC.2016.7598339},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/KarSRDM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/SinghKRDM16,
author = {Arvind Singh and
Monodeep Kar and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
editor = {William H. Robinson and
Swarup Bhunia and
Ryan Kastner},
title = {Integrated all-digital low-dropout regulator as a countermeasure to
power attack in encryption engines},
booktitle = {2016 {IEEE} International Symposium on Hardware Oriented Security
and Trust, {HOST} 2016, McLean, VA, USA, May 3-5, 2016},
pages = {145--148},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/HST.2016.7495573},
doi = {10.1109/HST.2016.7495573},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/SinghKRDM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KarSRDM16,
author = {Monodeep Kar and
Arvind Singh and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {What does ultra low power requirements mean for side-channel secure
cryptography?},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {686--689},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753359},
doi = {10.1109/ICCD.2016.7753359},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KarSRDM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KarSMRDM16,
author = {Monodeep Kar and
Arvind Singh and
Sanu Mathew and
Anand Rajan and
Vivek De and
Saibal Mukhopadhyay},
title = {Exploiting Fully Integrated Inductive Voltage Regulators to Improve
Side Channel Resistance of Encryption Engines},
booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics
and Design, {ISLPED} 2016, San Francisco Airport, CA, USA, August
08 - 10, 2016},
pages = {130--135},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2934583.2934607},
doi = {10.1145/2934583.2934607},
timestamp = {Tue, 06 Nov 2018 16:59:21 +0100},
biburl = {https://dblp.org/rec/conf/islped/KarSMRDM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChoKTAKRTKD16,
author = {Minki Cho and
Stephen T. Kim and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution
core using adaptive voltage scaling and dynamic power gating},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {152--153},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417952},
doi = {10.1109/ISSCC.2016.7417952},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ChoKTAKRTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DeBYLVMN16,
author = {Vivek De and
Kerry Bernstein and
Takefumi Yoshikawa and
Yusuf Leblebici and
Marian Verhelst and
Mahesh Mehendale and
Makoto Nagata},
title = {{F1:} Designing secure systems: Manufacturing, circuits and architectures},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {492--494},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7418121},
doi = {10.1109/ISSCC.2016.7418121},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DeBYLVMN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChoTKTKD16,
author = {Minki Cho and
Carlos Tokunaga and
Stephen T. Kim and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {Adaptive clocking with dynamic power gating for mitigating energy
efficiency {\&} performance impacts of fast voltage droop in a
22nm graphics execution core},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573529},
doi = {10.1109/VLSIC.2016.7573529},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChoTKTKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MathewSSAKAHCKD16,
author = {Sanu Mathew and
Sudhir Satpathy and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy and
Vivek De},
title = {A 4fJ/bit delay-hardened physically unclonable function circuit with
selective bit destabilization in 14nm tri-gate {CMOS}},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573554},
doi = {10.1109/VLSIC.2016.7573554},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MathewSSAKAHCKD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PaulHKMAGSMJVTD16,
author = {Somnath Paul and
Vinayak Honkote and
Ryan Gary Kim and
Turbo Majumder and
Paolo A. Aseron and
Vaughn Grossnickle and
Robert Sankman and
Debendra Mallik and
Sandeep Jain and
Sriram R. Vangal and
James W. Tschanz and
Vivek De},
title = {An energy harvesting wireless sensor node for IoT systems featuring
a near-threshold voltage {IA-32} microcontroller in 14nm tri-gate
{CMOS}},
booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
HI, USA, June 15-17, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSIC.2016.7573485},
doi = {10.1109/VLSIC.2016.7573485},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/PaulHKMAGSMJVTD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/DeKKLMW15,
author = {Vivek K. De and
Andrew B. Kahng and
Tanay Karnik and
Bao Liu and
Milad Maleki and
Lu Wang},
title = {Application-Specific Cross-Layer Optimization Based on Predictive
Variable-Latency {VLSI} Design},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {12},
number = {3},
pages = {21:1--21:19},
year = {2015},
url = {https://doi.org/10.1145/2746341},
doi = {10.1145/2746341},
timestamp = {Thu, 21 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jetc/DeKKLMW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DeKCRS15,
author = {Vivek De and
Stephen Kosonocky and
Jonathan Chang and
Yogesh K. Ramadass and
David Stoppa},
title = {Highlights of the {IEEE} {ISSCC} 2014 Processors, Digital, Memory,
Biomedical {\&} Next-Generation Systems Technologies, and Imagers,
MEMS, Medical {\&} Displays Sessions},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {4--9},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2379853},
doi = {10.1109/JSSC.2014.2379853},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DeKCRS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenAKSMHAKDB15,
author = {Gregory K. Chen and
Mark A. Anders and
Himanshu Kaul and
Sudhir Satpathy and
Sanu K. Mathew and
Steven Hsu and
Amit Agarwal and
Ram Krishnamurthy and
Vivek De and
Shekhar Borkar},
title = {A 340 mV-to-0.9 {V} 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched
16 {\texttimes} 16 Network-on-Chip in 22 nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {59--67},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2369508},
doi = {10.1109/JSSC.2014.2369508},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChenAKSMHAKDB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JainKVRTD15,
author = {Rinkle Jain and
Stephen T. Kim and
Vaibhav A. Vaidya and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {Conductance Modulation Techniques in Switched-Capacitor {DC-DC} Converter
for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate
{CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {8},
pages = {1809--1819},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2413952},
doi = {10.1109/JSSC.2015.2413952},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JainKVRTD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/ChoTKTD15,
author = {Minki Cho and
Carlos Tokunaga and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate
{CMOS}},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338419},
doi = {10.1109/CICC.2015.7338419},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/ChoTKTD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KumarVKKMWTPRD15,
author = {Pavan Kumar and
Vaibhav A. Vaidya and
Harish Krishnamurthy and
Stephen T. Kim and
George E. Matthew and
Sheldon Weng and
Bharani Thiruvengadam and
Wayne Proefrock and
Krishnan Ravichandran and
Vivek De},
title = {A 0.4V{\(\sim\)}1V 0.2A/mm\({}^{\mbox{2}}\) 70{\%} efficient 500MHz
fully integrated digitally controlled 3-level buck voltage regulator
with on-die high density {MIM} capacitor in 22nm tri-gate {CMOS}},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338479},
doi = {10.1109/CICC.2015.7338479},
timestamp = {Wed, 05 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KumarVKKMWTPRD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/De15,
author = {Vivek De},
editor = {Diana Marculescu and
Frank Liu},
title = {Fine-Grain Power Management in Manycore Processor and System-on-Chip
(SoC) Designs},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {159--164},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372564},
doi = {10.1109/ICCAD.2015.7372564},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/De15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimSMJRTAKRTKD15,
author = {Stephen T. Kim and
Yi{-}Chun Shih and
Kaushik Mazumdar and
Rinkle Jain and
Joseph F. Ryan and
Carlos Tokunaga and
Charles Augustine and
Jaydeep P. Kulkarni and
Krishnan Ravichandran and
James W. Tschanz and
Muhammad M. Khellah and
Vivek De},
title = {8.6 Enabling wide autonomous {DVFS} in a 22nm graphics execution core
using a digitally controlled hybrid LDO/switched-capacitor {VR} with
fast droop mitigation},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062972},
doi = {10.1109/ISSCC.2015.7062972},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimSMJRTAKRTKD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KulkarniTANATD15,
author = {Jaydeep P. Kulkarni and
Carlos Tokunaga and
Paolo A. Aseron and
Trang Nguyen and
Charles Augustine and
James W. Tschanz and
Vivek De},
title = {4.7 {A} 409GOPS/W adaptive and resilient domino register file in 22nm
tri-gate {CMOS} featuring in-situ timing margin and error detection
for tolerance to within-die variation, voltage droop, temperature
and aging},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062936},
doi = {10.1109/ISSCC.2015.7062936},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KulkarniTANATD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JainGKKKTD14,
author = {Rinkle Jain and
Bibiche M. Geuskens and
Stephen T. Kim and
Muhammad M. Khellah and
Jaydeep Kulkarni and
James W. Tschanz and
Vivek De},
title = {A 0.45-1 {V} Fully-Integrated Distributed Switched Capacitor {DC-DC}
Converter With High Density {MIM} Capacitor in 22 nm Tri-Gate {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {4},
pages = {917--927},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2297402},
doi = {10.1109/JSSC.2013.2297402},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JainGKKKTD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KarnikTBHVDB14,
author = {Tanay Karnik and
James W. Tschanz and
Nitin Borkar and
Jason Howard and
Sriram R. Vangal and
Vivek De and
Shekhar Borkar},
title = {Resiliency for many-core system on a chip},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {388--389},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742921},
doi = {10.1109/ASPDAC.2014.6742921},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KarnikTBHVDB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/De14,
author = {Vivek De},
title = {Energy efficient computing in nanoscale {CMOS:} Challenges and opportunities},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2014, KaoHsiung,
Taiwan, November 10-12, 2014},
pages = {121--124},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASSCC.2014.7008875},
doi = {10.1109/ASSCC.2014.7008875},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/De14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/JainKVTRD14,
author = {Rinkle Jain and
Stephen T. Kim and
Vaibhav A. Vaidya and
James W. Tschanz and
Krishnan Ravichandran and
Vivek De},
title = {Conductance modulation techniques in switched-capacitor {DC-DC} converter
for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate
{CMOS}},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6946052},
doi = {10.1109/CICC.2014.6946052},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/JainKVTRD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KarLWDM14,
author = {Monodeep Kar and
Denny Lie and
Marilyn Wolf and
Vivek De and
Saibal Mukhopadhyay},
title = {Impact of inductive integrated voltage regulator on the power attack
vulnerability of encryption engines: {A} simulation study},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6946135},
doi = {10.1109/CICC.2014.6946135},
timestamp = {Wed, 21 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KarLWDM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/PawlowskiCCTDFQBC14,
author = {Robert Pawlowski and
Joseph Crop and
Minki Cho and
James W. Tschanz and
Vivek De and
Thomas Fairbanks and
Heather Quinn and
Shekhar Borkar and
Patrick Yin Chiang},
title = {Characterization of radiation-induced {SRAM} and logic soft errors
from 0.33V to 1.0V in 65nm {CMOS}},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6946138},
doi = {10.1109/CICC.2014.6946138},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/PawlowskiCCTDFQBC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/VangalJD14,
author = {Sriram R. Vangal and
Shailendra Jain and
Vivek De},
title = {A solar-powered 280mV-to-1.2V wide-operating-range {IA-32} processor},
booktitle = {2014 {IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2014, Austin, TX, USA, May 28-30, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ICICDT.2014.6838610},
doi = {10.1109/ICICDT.2014.6838610},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/VangalJD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TokunagaRAKSKJB14,
author = {Carlos Tokunaga and
Joseph F. Ryan and
Charles Augustine and
Jaydeep P. Kulkarni and
Yi{-}Chun Shih and
Stephen T. Kim and
Rinkle Jain and
Keith A. Bowman and
Arijit Raychowdhury and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {5.7 {A} graphics execution core in 22nm {CMOS} featuring adaptive
clocking, selective boosting and state-retentive sleep},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {108--109},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757359},
doi = {10.1109/ISSCC.2014.6757359},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TokunagaRAKSKJB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChenAKSMHAKBD14,
author = {Gregory K. Chen and
Mark A. Anders and
Himanshu Kaul and
Sudhir Satpathy and
Sanu K. Mathew and
Steven K. Hsu and
Amit Agarwal and
Ram K. Krishnamurthy and
Shekhar Borkar and
Vivek De},
title = {16.1 {A} 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched
16{\texttimes}16 network-on-chip in 22nm tri-gate {CMOS}},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {276--277},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757432},
doi = {10.1109/ISSCC.2014.6757432},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ChenAKSMHAKBD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MathewSAKHACPKD14,
author = {Sanu K. Mathew and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Steven K. Hsu and
Amit Agarwal and
Gregory K. Chen and
Rachael J. Parker and
Ram K. Krishnamurthy and
Vivek De},
title = {16.2 {A} 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable
function circuit for 100{\%} stable secure key generation in 22nm
{CMOS}},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {278--279},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757433},
doi = {10.1109/ISSCC.2014.6757433},
timestamp = {Mon, 08 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MathewSAKHACPKD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DeK14,
author = {Vivek De and
Hideyuki Kabuo},
title = {Foreword: Welcome to the 2014 Symposium on {VLSI} Circuits},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
Honolulu, HI, USA, June 10-13, 2014},
pages = {1--2},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSIC.2014.6858355},
doi = {10.1109/VLSIC.2014.6858355},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/DeK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KrishnamurthyVK14,
author = {Harish Krishnamurthy and
Vaibhav A. Vaidya and
Pavan Kumar and
George E. Matthew and
Sheldon Weng and
Bharani Thiruvengadam and
Wayne Proefrock and
Krishnan Ravichandran and
Vivek De},
title = {A 500 MHz, 68{\%} efficient, fully on-die digitally controlled buck
Voltage Regulator on 22nm Tri-Gate {CMOS}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2014, Digest of Technical Papers,
Honolulu, HI, USA, June 10-13, 2014},
pages = {1--2},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSIC.2014.6858438},
doi = {10.1109/VLSIC.2014.6858438},
timestamp = {Wed, 05 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KrishnamurthyVK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BowmanTTKD13,
author = {Keith A. Bowman and
Carlos Tokunaga and
James W. Tschanz and
Tanay Karnik and
Vivek K. De},
title = {Adaptive and Resilient Circuits for Dynamic Variation Tolerance},
journal = {{IEEE} Des. Test},
volume = {30},
number = {6},
pages = {8--17},
year = {2013},
url = {https://doi.org/10.1109/MDAT.2013.2267958},
doi = {10.1109/MDAT.2013.2267958},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BowmanTTKD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DeK13,
author = {Vivek De and
Hideyuki Kabuo},
title = {Introduction to the Special Issue on the 2012 Symposium on {VLSI}
Circuits},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {4},
pages = {895--896},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2239171},
doi = {10.1109/JSSC.2013.2239171},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DeK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BowmanTKDT13,
author = {Keith A. Bowman and
Carlos Tokunaga and
Tanay Karnik and
Vivek K. De and
James W. Tschanz},
title = {A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply
Voltage Droop Tolerance},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {4},
pages = {907--916},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2237972},
doi = {10.1109/JSSC.2013.2237972},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BowmanTKDT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/RaychowdhuryTBDTD13,
author = {Arijit Raychowdhury and
Carlos Tokunaga and
Willem Marco Beltman and
Michael Deisher and
James W. Tschanz and
Vivek De},
title = {A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware
System-On-Chip Applications in 32-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {8},
pages = {1963--1969},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2258827},
doi = {10.1109/JSSC.2013.2258827},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/RaychowdhuryTBDTD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/De13,
author = {Vivek De},
title = {Keynote: Variation-tolerant adaptive and resilient designs in nanoscale
{CMOS}},
booktitle = {19th {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2013, Santa Monica, CA, USA, May 19-22, 2013},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ASYNC.2013.35},
doi = {10.1109/ASYNC.2013.35},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/De13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/De13,
author = {Vivek De},
editor = {Enrico Macii},
title = {Near-threshold voltage design in nanoscale {CMOS}},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {612},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.134},
doi = {10.7873/DATE.2013.134},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/De13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpdc/De13,
author = {Vivek De},
editor = {Nathan DeBardeleben and
Jon Stearley and
Franck Cappello},
title = {Circuits for resilient systems},
booktitle = {Proceedings of the 3rd Workshop on Fault-tolerance for {HPC} at extreme
scale, jointly held with the 22nd International Symposium on High-Performance
Parallel and Distributed Computing, HPDC'13, New York, NY, USA, June
18, 2013},
pages = {11--12},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2465813.2465815},
doi = {10.1145/2465813.2465815},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpdc/De13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/NagataD12,
author = {Makoto Nagata and
Vivek De},
title = {Introduction to the Special Issue on the 2011 Symposium on {VLSI}
Circuits},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {4},
pages = {795--796},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2185357},
doi = {10.1109/JSSC.2012.2185357},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/NagataD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/RaychowdhuryTBDTD12,
author = {Arijit Raychowdhury and
Carlos Tokunaga and
Willem Marco Beltman and
Michael Deisher and
James W. Tschanz and
Vivek De},
title = {A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware
System-on-Chip applications in 32nm {CMOS}},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330651},
doi = {10.1109/CICC.2012.6330651},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/RaychowdhuryTBDTD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/NicolaidisAZZKBTLTRKKDA12,
author = {Michael Nicolaidis and
Lorena Anghel and
Nacer{-}Eddine Zergainoh and
Yervant Zorian and
Tanay Karnik and
Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Carlos Tokunaga and
Arijit Raychowdhury and
Muhammad M. Khellah and
Jaydeep Kulkarni and
Vivek De and
Dimiter Avresky},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {Design for test and reliability in ultimate {CMOS}},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {677--682},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176556},
doi = {10.1109/DATE.2012.6176556},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/NicolaidisAZZKBTLTRKKDA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/JainKYASRMSKKREHVDRAWBDB12,
author = {Shailendra Jain and
Surhud Khare and
Satish Yada and
V. Ambili and
Praveen Salihundam and
Shiva Ramani and
Sriram Muthukumar and
M. Srinivasan and
Arun Kumar and
Shasi Kumar and
Rajaraman Ramanarayanan and
Vasantha Erraguntla and
Jason Howard and
Sriram R. Vangal and
Saurabh Dighe and
Gregory Ruhl and
Paolo A. Aseron and
Howard Wilson and
Nitin Borkar and
Vivek De and
Shekhar Borkar},
title = {A 280mV-to-1.2V wide-operating-range {IA-32} processor in 32nm {CMOS}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {66--68},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176932},
doi = {10.1109/ISSCC.2012.6176932},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/JainKYASRMSKKREHVDRAWBDB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KulkarniGKKTD12,
author = {Jaydeep Kulkarni and
Bibiche M. Geuskens and
Tanay Karnik and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Capacitive-coupling wordline boosting with self-induced {VCC} collapse
for write {VMIN} reduction in 22-nm 8T {SRAM}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {234--236},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176990},
doi = {10.1109/ISSCC.2012.6176990},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KulkarniGKKTD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BowmanTKDT12,
author = {Keith A. Bowman and
Carlos Tokunaga and
Tanay Karnik and
Vivek K. De and
Jim Tschanz},
title = {A 22nm dynamically adaptive clock distribution for voltage droop tolerance},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {94--95},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243806},
doi = {10.1109/VLSIC.2012.6243806},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/BowmanTKDT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/RaychowdhurySTD12,
author = {Arijit Raychowdhury and
Dinesh Somasekhar and
James W. Tschanz and
Vivek De},
title = {A fully-digital phase-locked low dropout regulator in 32nm {CMOS}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {148--149},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243833},
doi = {10.1109/VLSIC.2012.6243833},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/RaychowdhurySTD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/RaychowdhuryTBLAKGTWKD11,
author = {Arijit Raychowdhury and
Jim Tschanz and
Keith A. Bowman and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek De},
title = {Error Detection and Correction in Microprocessor Core and Memory Due
to Fast Dynamic Voltage Droops},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {1},
number = {3},
pages = {208--217},
year = {2011},
url = {https://doi.org/10.1109/JETCAS.2011.2167070},
doi = {10.1109/JETCAS.2011.2167070},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/RaychowdhuryTBLAKGTWKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HowardDVRBJEKRGDLSBDW11,
author = {Jason Howard and
Saurabh Dighe and
Sriram R. Vangal and
Gregory Ruhl and
Nitin Borkar and
Shailendra Jain and
Vasantha Erraguntla and
Michael Konow and
Michael Riepen and
Matthias Gries and
Guido Droege and
Tor Lund{-}Larsen and
Sebastian Steibl and
Shekhar Borkar and
Vivek K. De and
Rob F. Van der Wijngaart},
title = {A 48-Core {IA-32} Processor in 45 nm {CMOS} Using On-Die Message-Passing
and {DVFS} for Performance and Power Scaling},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {173--183},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2079450},
doi = {10.1109/JSSC.2010.2079450},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HowardDVRBJEKRGDLSBDW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DigheVAKJBHTEBDB11,
author = {Saurabh Dighe and
Sriram R. Vangal and
Paolo A. Aseron and
Shasi Kumar and
Tiju Jacob and
Keith A. Bowman and
Jason Howard and
James W. Tschanz and
Vasantha Erraguntla and
Nitin Borkar and
Vivek K. De and
Shekhar Borkar},
title = {Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With
Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS
Processor},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {184--193},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2080550},
doi = {10.1109/JSSC.2010.2080550},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DigheVAKJBHTEBDB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BowmanTLAKRGTWKD11,
author = {Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Arijit Raychowdhury and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek K. De},
title = {A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {194--208},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2089657},
doi = {10.1109/JSSC.2010.2089657},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BowmanTLAKRGTWKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/RaychowdhuryGBTLKKD11,
author = {Arijit Raychowdhury and
Bibiche M. Geuskens and
Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Tanay Karnik and
Muhammad M. Khellah and
Vivek K. De},
title = {Tunable Replica Bits for Dynamic Variation Tolerance in 8T {SRAM}
Arrays},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {4},
pages = {797--805},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2108141},
doi = {10.1109/JSSC.2011.2108141},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/RaychowdhuryGBTLKKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/BowmanTTRKGLAKD11,
author = {Keith A. Bowman and
Carlos Tokunaga and
James W. Tschanz and
Arijit Raychowdhury and
Muhammad M. Khellah and
Bibiche M. Geuskens and
Shih{-}Lien Lu and
Paolo A. Aseron and
Tanay Karnik and
Vivek K. De},
title = {All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug
and Adaptive Clock Control},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {58-I},
number = {9},
pages = {2017--2025},
year = {2011},
url = {https://doi.org/10.1109/TCSI.2011.2163893},
doi = {10.1109/TCSI.2011.2163893},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/BowmanTTRKGLAKD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/De11,
author = {Vivek De},
editor = {Rakesh Patel and
Tom Andre and
Aurangzeb Khan},
title = {Energy efficient designs with wide dynamic range},
booktitle = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
Jose, CA, USA, Sept. 19-21, 2011},
pages = {1},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CICC.2011.6055377},
doi = {10.1109/CICC.2011.6055377},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/De11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TschanzBKWGSRKTLKD10,
author = {James W. Tschanz and
Keith A. Bowman and
Muhammad M. Khellah and
Chris Wilkerson and
Bibiche M. Geuskens and
Dinesh Somasekhar and
Arijit Raychowdhury and
Jaydeep Kulkarni and
Carlos Tokunaga and
Shih{-}Lien Lu and
Tanay Karnik and
Vivek De},
title = {Resilient design in scaled {CMOS} for energy efficiency},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {625},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419812},
doi = {10.1109/ASPDAC.2010.5419812},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/TschanzBKWGSRKTLKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/BowmanTTRKGLAKD10,
author = {Keith A. Bowman and
Carlos Tokunaga and
James W. Tschanz and
Arijit Raychowdhury and
Muhammad M. Khellah and
Bibiche M. Geuskens and
Shih{-}Lien Lu and
Paolo A. Aseron and
Tanay Karnik and
Vivek De},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Dynamic variation monitor for measuring the impact of voltage droops
on microprocessor clock frequency},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617415},
doi = {10.1109/CICC.2010.5617415},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/BowmanTTRKGLAKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/GeuskensKKKD10,
author = {Bibiche M. Geuskens and
Muhammad M. Khellah and
Jaydeep Kulkarni and
Tanay Karnik and
Vivek De},
editor = {Jacqueline Snyder and
Rakesh Patel and
Tom Andre},
title = {Opportunities for {PMOS} read and write ports in low voltage dual-port
8T bit cell arrays},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
California, USA, 19-22 September, 2010, Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CICC.2010.5617441},
doi = {10.1109/CICC.2010.5617441},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/GeuskensKKKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/BowmanTLAKRGTWKD10,
author = {Keith A. Bowman and
James W. Tschanz and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Arijit Raychowdhury and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek De},
editor = {Vojin G. Oklobdzija and
Barry Pangle and
Naehyuck Chang and
Naresh R. Shanbhag and
Chris H. Kim},
title = {Resilient microprocessor design for high performance {\&} energy
efficiency},
booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics
and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
pages = {355--356},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1840845.1840919},
doi = {10.1145/1840845.1840919},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/BowmanTLAKRGTWKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HowardDHVFRJWBSPJJYMSEKRDLGAHLSBDWM10,
author = {Jason Howard and
Saurabh Dighe and
Yatin Vasant Hoskote and
Sriram R. Vangal and
David Finan and
Gregory Ruhl and
David Jenkins and
Howard Wilson and
Nitin Borkar and
Gerhard Schrom and
Fabric Pailet and
Shailendra Jain and
Tiju Jacob and
Satish Yada and
Sraven Marella and
Praveen Salihundam and
Vasantha Erraguntla and
Michael Konow and
Michael Riepen and
Guido Droege and
Joerg Lindemann and
Matthias Gries and
Thomas Apel and
Kersten Henriss and
Tor Lund{-}Larsen and
Sebastian Steibl and
Shekhar Borkar and
Vivek De and
Rob F. Van der Wijngaart and
Timothy G. Mattson},
title = {A 48-Core {IA-32} message-passing processor with {DVFS} in 45nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {108--109},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5434077},
doi = {10.1109/ISSCC.2010.5434077},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HowardDHVFRJWBSPJJYMSEKRDLGAHLSBDWM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/DigheVAKJBHTEBDB10,
author = {Saurabh Dighe and
Sriram R. Vangal and
Paolo A. Aseron and
Shasi Kumar and
Tiju Jacob and
Keith A. Bowman and
Jason Howard and
James W. Tschanz and
Vasantha Erraguntla and
Nitin Borkar and
Vivek De and
Shekhar Borkar},
title = {Within-die variation-aware dynamic-voltage-frequency scaling core
mapping and thread hopping for an 80-core processor},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {174--175},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433997},
doi = {10.1109/ISSCC.2010.5433997},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/DigheVAKJBHTEBDB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TschanzBLAKRGTWKD10,
author = {James W. Tschanz and
Keith A. Bowman and
Shih{-}Lien Lu and
Paolo A. Aseron and
Muhammad M. Khellah and
Arijit Raychowdhury and
Bibiche M. Geuskens and
Carlos Tokunaga and
Chris Wilkerson and
Tanay Karnik and
Vivek De},
title = {A 45nm resilient and adaptive microprocessor core for dynamic variation
tolerance},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {282--283},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433922},
doi = {10.1109/ISSCC.2010.5433922},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TschanzBLAKRGTWKD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RaychowdhuryGKTBKLDK10,
author = {Arijit Raychowdhury and
Bibiche M. Geuskens and
Jaydeep Kulkarni and
James W. Tschanz and
Keith A. Bowman and
Tanay Karnik and
Shih{-}Lien Lu and
Vivek De and
Muhammad M. Khellah},
title = {PVT-and-aging adaptive wordline boosting for 8T {SRAM} power reduction},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {352--353},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433815},
doi = {10.1109/ISSCC.2010.5433815},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/RaychowdhuryGKTBKLDK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BowmanTKLWLKD09,
author = {Keith A. Bowman and
James W. Tschanz and
Nam{-}Sung Kim and
Janice C. Lee and
Chris Wilkerson and
Shih{-}Lien Lu and
Tanay Karnik and
Vivek K. De},
title = {Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic
Variation Tolerance},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {49--63},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2007148},
doi = {10.1109/JSSC.2008.2007148},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BowmanTKLWLKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SomasekharYALKH09,
author = {Dinesh Somasekhar and
Yibin Ye and
Paolo A. Aseron and
Shih{-}Lien Lu and
Muhammad M. Khellah and
Jason Howard and
Gregory Ruhl and
Tanay Karnik and
Shekhar Borkar and
Vivek K. De and
Ali Keshavarzi},
title = {2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth
in a 65 nm Logic Process Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {1},
pages = {174--185},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2008.2007155},
doi = {10.1109/JSSC.2008.2007155},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SomasekharYALKH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KhellahKYSKBPHC09,
author = {Muhammad M. Khellah and
Nam{-}Sung Kim and
Yibin Ye and
Dinesh Somasekhar and
Tanay Karnik and
Nitin Borkar and
Gunjan Pandya and
Fatih Hamzaoglu and
Tom Coan and
Yih Wang and
Kevin Zhang and
Clair Webb and
Vivek De},
title = {Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays
With Diffusion-Notch-Free {(DNF)} 6T {SRAM} Cells and Dynamic Multi-Vcc
Circuits},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {4},
pages = {1199--1208},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2014015},
doi = {10.1109/JSSC.2009.2014015},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KhellahKYSKBPHC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/KhalilKKIKD09,
author = {DiaaEldin Khalil and
Muhammad M. Khellah and
Nam{-}Sung Kim and
Yehea I. Ismail and
Tanay Karnik and
Vivek De},
title = {{SRAM} dynamic stability estimation using {MPFP} and its applications},
journal = {Microelectron. J.},
volume = {40},
number = {11},
pages = {1523--1530},
year = {2009},
url = {https://doi.org/10.1016/j.mejo.2009.01.015},
doi = {10.1016/J.MEJO.2009.01.015},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/KhalilKKIKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaIKD09,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {{SSMCB:} Low-Power Variation-Tolerant Source-Synchronous Multicycle
Bus},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {2},
pages = {384--394},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2001805},
doi = {10.1109/TCSI.2008.2001805},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaIKD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaIKTD09,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Serial-Link Bus: {A} Low-Power On-Chip Bus Architecture},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {9},
pages = {2020--2032},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2010155},
doi = {10.1109/TCSI.2008.2010155},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaIKTD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/BowmanTWLKDB09,
author = {Keith A. Bowman and
James W. Tschanz and
Chris Wilkerson and
Shih{-}Lien Lu and
Tanay Karnik and
Vivek De and
Shekhar Y. Borkar},
title = {Circuit techniques for dynamic variation tolerance},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {4--7},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1629915},
doi = {10.1145/1629911.1629915},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/BowmanTWLKDB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/XuHWAHPSTDKT08,
author = {Jianping Xu and
Peter Hazucha and
Zuoguo Wu and
Paolo A. Aseron and
Mingwei Huang and
Fabrice Paillet and
Gerhard Schrom and
James W. Tschanz and
Vivek De and
Tanay Karnik and
Greg Taylor},
title = {A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance
Reduction},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {1},
pages = {61--68},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2007.913155},
doi = {10.1109/JSSC.2007.913155},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/XuHWAHPSTDKT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaKTYKBNID08,
author = {Maged Ghoneima and
Muhammad M. Khellah and
James W. Tschanz and
Yibin Ye and
Nasser A. Kurd and
Javed Barkatullah and
Srikanth Nimmagadda and
Yehea I. Ismail and
Vivek K. De},
title = {Skewed Repeater Bus: {A} Low-Power Scheme for On-Chip Buses},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {55-I},
number = {7},
pages = {1904--1910},
year = {2008},
url = {https://doi.org/10.1109/TCSI.2008.928527},
doi = {10.1109/TCSI.2008.928527},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaKTYKBNID08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhalilKKIKD08,
author = {D. E. Khalil and
Muhammad M. Khellah and
Nam{-}Sung Kim and
Yehea I. Ismail and
Tanay Karnik and
Vivek K. De},
title = {Accurate Estimation of {SRAM} Dynamic Stability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {12},
pages = {1639--1647},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2001941},
doi = {10.1109/TVLSI.2008.2001941},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhalilKKIKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/DadgourDB08,
author = {Hamed F. Dadgour and
Vivek De and
Kaustav Banerjee},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Statistical modeling of metal-gate work-function variability in emerging
device technologies and implications for circuit design},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {270--277},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681585},
doi = {10.1109/ICCAD.2008.4681585},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/DadgourDB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KhalilIKKD08,
author = {DiaaEldin Khalil and
Yehea I. Ismail and
Muhammad M. Khellah and
Tanay Karnik and
Vivek De},
title = {Analytical Model for the Propagation Delay of Through Silicon Vias},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {553--556},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479795},
doi = {10.1109/ISQED.2008.4479795},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KhalilIKKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SomasekharYALKHRKBDK08,
author = {Dinesh Somasekhar and
Yibin Ye and
Paolo A. Aseron and
Shih{-}Lien Lu and
Muhammad M. Khellah and
Jason Howard and
Gregory Ruhl and
Tanay Karnik and
Shekhar Y. Borkar and
Vivek De and
Ali Keshavarzi},
title = {2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm
Logic Process},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {274--275},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523163},
doi = {10.1109/ISSCC.2008.4523163},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SomasekharYALKHRKBDK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BowmanTKLWLKD08,
author = {Keith A. Bowman and
James W. Tschanz and
Nam{-}Sung Kim and
Janice C. Lee and
Chris Wilkerson and
Shih{-}Lien Lu and
Tanay Karnik and
Vivek K. De},
title = {Energy-Efficient and Metastability-Immune Timing-Error Detection and
Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {402--403},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523227},
doi = {10.1109/ISSCC.2008.4523227},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BowmanTKLWLKD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KhellahSYKHRSTB07,
author = {Muhammad M. Khellah and
Dinesh Somasekhar and
Yibin Ye and
Nam{-}Sung Kim and
Jason Howard and
Gregory Ruhl and
Murad Sunna and
James W. Tschanz and
Nitin Borkar and
Fatih Hamzaoglu and
Gunjan Pandya and
Ali Farhang and
Kevin Zhang and
Vivek De},
title = {A 256-Kb Dual-V\({}_{\mbox{CC}}\) {SRAM} Building Block in 65-nm {CMOS}
Process With Actively Clamped Sleep Transistor},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {1},
pages = {233--242},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2006.888357},
doi = {10.1109/JSSC.2006.888357},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KhellahSYKHRSTB07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AziziKDN07,
author = {Navid Azizi and
Muhammad M. Khellah and
Vivek De and
Farid N. Najm},
title = {Variations-Aware Low-Power Design and Block Clustering With Voltage
Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {15},
number = {7},
pages = {746--757},
year = {2007},
url = {https://doi.org/10.1109/TVLSI.2007.899226},
doi = {10.1109/TVLSI.2007.899226},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AziziKDN07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GhoneimaIKD07,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip
Interconnect Scheme},
journal = {{VLSI} Design},
volume = {2007},
pages = {95402:1--95402:12},
year = {2007},
url = {https://doi.org/10.1155/2007/95402},
doi = {10.1155/2007/95402},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GhoneimaIKD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/BurnsKMBTD07,
author = {Steven M. Burns and
Mahesh Ketkar and
Noel Menezes and
Keith A. Bowman and
James W. Tschanz and
Vivek De},
title = {Comparative Analysis of Conventional and Statistical Design Techniques},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {238--243},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278539},
doi = {10.1145/1278480.1278539},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/BurnsKMBTD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/XuHHAPSTZDKT07,
author = {Jianping Xu and
Peter Hazucha and
Mingwei Huang and
Paolo A. Aseron and
Fabrice Paillet and
Gerhard Schrom and
James W. Tschanz and
Cangsang Zhao and
Vivek De and
Tanay Karnik and
Greg Taylor},
title = {On-Die Supply-Resonance Suppression Using Band-Limited Active Damping},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {286--603},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373406},
doi = {10.1109/ISSCC.2007.373406},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/XuHHAPSTZDKT07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TschanzKDHRVNHWLSTSTFKBAD07,
author = {James W. Tschanz and
Nam{-}Sung Kim and
Saurabh Dighe and
Jason Howard and
Gregory Ruhl and
Sriram R. Vangal and
Siva G. Narendra and
Yatin Hoskote and
Howard Wilson and
Carol Lam and
Matthew Shuman and
Carlos Tokunaga and
Dinesh Somasekhar and
Stephen Tang and
David Finan and
Tanay Karnik and
Nitin Borkar and
Nasser A. Kurd and
Vivek De},
title = {Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic
Temperature-Voltage Variations and Aging},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {292--604},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373409},
doi = {10.1109/ISSCC.2007.373409},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/TschanzKDHRVNHWLSTSTFKBAD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/UnsalTBDVGE06,
author = {Osman S. Unsal and
James W. Tschanz and
Keith A. Bowman and
Vivek De and
Xavier Vera and
Antonio Gonz{\'{a}}lez and
Oguz Ergin},
title = {Impact of Parameter Variations on Circuits and Microarchitecture},
journal = {{IEEE} Micro},
volume = {26},
number = {6},
pages = {30--39},
year = {2006},
url = {https://doi.org/10.1109/MM.2006.122},
doi = {10.1109/MM.2006.122},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/UnsalTBDVGE06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoneimaIKTD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Formal derivation of optimal active shielding for low-power on-chip
buses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {5},
pages = {821--836},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855974},
doi = {10.1109/TCAD.2005.855974},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoneimaIKTD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GhoneimaIKTD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Reducing the Effective Coupling Capacitance in Buses Using Threshold
Voltage Adjustment Techniques},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {53-I},
number = {9},
pages = {1928--1933},
year = {2006},
url = {https://doi.org/10.1109/TCSI.2006.879054},
doi = {10.1109/TCSI.2006.879054},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/GhoneimaIKTD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GhoneimaIKD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {Reducing the data switching activity of serialized datastreams},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692760},
doi = {10.1109/ISCAS.2006.1692760},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GhoneimaIKD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YeKSD06,
author = {Yibin Ye and
Muhammad M. Khellah and
Dinesh Somasekhar and
Vivek De},
title = {Evaluation of differential vs. single-ended sensing and asymmetric
cells in 90 nm logic technology for on-chip caches},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692747},
doi = {10.1109/ISCAS.2006.1692747},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/YeKSD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/BowmanTKGID06,
author = {Keith A. Bowman and
James W. Tschanz and
Muhammad M. Khellah and
Maged Ghoneima and
Yehea I. Ismail and
Vivek De},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {Time-borrowing multi-cycle on-chip interconnects for delay variation
tolerance},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {79--84},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165592},
doi = {10.1145/1165573.1165592},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/BowmanTKGID06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GhoneimaIKD06,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
Vivek De},
title = {Reducing the Data Switching Activity on Serial Link Buses},
booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED}
2006), 27-29 March 2006, San Jose, CA, {USA}},
pages = {425--432},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISQED.2006.111},
doi = {10.1109/ISQED.2006.111},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/GhoneimaIKD06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhellahKHRYTSBH06,
author = {Muhammad M. Khellah and
Nam{-}Sung Kim and
Jason Howard and
Gregory Ruhl and
Yibin Ye and
James W. Tschanz and
Dinesh Somasekhar and
Nitin Borkar and
Fatih Hamzaoglu and
Gunjan Pandya and
Ali Farhang and
Kevin Zhang and
Vivek De},
title = {A 4.2GHz 0.3mm2 256kb Dual-V\({}_{\mbox{cc}}\) {SRAM} Building Block
in 65nm {CMOS}},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {2572--2581},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696323},
doi = {10.1109/ISSCC.2006.1696323},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhellahKHRYTSBH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AshoueiCSDM06,
author = {Maryam Ashouei and
Abhijit Chatterjee and
Adit D. Singh and
Vivek De and
T. M. Mak},
title = {Statistical Estimation of Correlated Leakage Power Variation and Its
Application to Leakage-Aware Design},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {606--612},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.152},
doi = {10.1109/VLSID.2006.152},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AshoueiCSDM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HazuchaSHBHDNGK05,
author = {Peter Hazucha and
Gerhard Schrom and
Jaehong Hahn and
Bradley A. Bloechel and
Paul Hack and
Gregory E. Dermer and
Siva G. Narendra and
Donald S. Gardner and
Tanay Karnik and
Vivek De and
Shekhar Borkar},
title = {A 233-MHz 80{\%}-87{\%} efficient four-phase {DC-DC} converter utilizing
air-core inductors on package},
journal = {{IEEE} J. Solid State Circuits},
volume = {40},
number = {4},
pages = {838--845},
year = {2005},
url = {https://doi.org/10.1109/JSSC.2004.842837},
doi = {10.1109/JSSC.2004.842837},
timestamp = {Tue, 19 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HazuchaSHBHDNGK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/KursunDFN05,
author = {Volkan Kursun and
Vivek De and
Eby G. Friedman and
Siva G. Narendra},
title = {Monolithic voltage conversion in low-voltage {CMOS} technologies},
journal = {Microelectron. J.},
volume = {36},
number = {9},
pages = {863--867},
year = {2005},
url = {https://doi.org/10.1016/j.mejo.2005.03.008},
doi = {10.1016/J.MEJO.2005.03.008},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/KursunDFN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AziziKDN05,
author = {Navid Azizi and
Muhammad M. Khellah and
Vivek De and
Farid N. Najm},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Variations-aware low-power design with voltage scaling},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {529--534},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065717},
doi = {10.1145/1065579.1065717},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AziziKDN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/TschanzBD05,
author = {James W. Tschanz and
Keith A. Bowman and
Vivek De},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Variation-tolerant circuits: circuit solutions and techniques},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {762--763},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065780},
doi = {10.1145/1065579.1065780},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/TschanzBD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SomasekharLBDLBD05,
author = {Dinesh Somasekhar and
Shih{-}Lien Lu and
Bradley A. Bloechel and
Greg Dermer and
Konrad Lai and
Sjeljar Borkar and
Vivek De},
editor = {Laurent Fesquet and
Andreas Kaiser and
Sorin Cristoloveanu and
Michel Brillou{\"{e}}t},
title = {A 10Mbit, 15GBytes/sec bandwidth 1T {DRAM} chip with planar {MOS}
storage capacitor in an unmodified 150nm logic process for high-density
on-chip memory applications},
booktitle = {Proceedings of the 31st European Solid-State Circuits Conference,
{ESSCIRC} 2005, Grenoble, France, 12-16 September 2005},
pages = {355--358},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ESSCIR.2005.1541633},
doi = {10.1109/ESSCIR.2005.1541633},
timestamp = {Fri, 28 Apr 2023 15:39:25 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/SomasekharLBDLBD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SuarisKBDM05,
author = {Peter Suaris and
Taeho Kgil and
Keith A. Bowman and
Vivek De and
Trevor N. Mudge},
title = {Total power-optimal pipelining and parallel processing under process
variations in nanometer technology},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {535--540},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560125},
doi = {10.1109/ICCAD.2005.1560125},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SuarisKBDM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/GhoneimaIKTD05,
author = {Maged Ghoneima and
Yehea I. Ismail and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De},
title = {Serial-link bus: a low-power on-chip bus architecture},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {541--546},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560126},
doi = {10.1109/ICCAD.2005.1560126},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/GhoneimaIKTD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/AshoueiCSD05,
author = {Maryam Ashouei and
Abhijit Chatterjee and
Adit D. Singh and
Vivek De},
title = {A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization
in Nanometer {CMOS}},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {567--573},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.6},
doi = {10.1109/ICCD.2005.6},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/AshoueiCSD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TschanzNKD05,
author = {James W. Tschanz and
Siva G. Narendra and
Ali Keshavarzi and
Vivek De},
title = {Adaptive circuit techniques to minimize variation impacts on microprocessor
performance and power},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {9--12},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464511},
doi = {10.1109/ISCAS.2005.1464511},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/TschanzNKD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KursunSDFN05,
author = {Volkan Kursun and
Gerhard Schrom and
Vivek De and
Eby G. Friedman and
Siva G. Narendra},
title = {Cascode buffer for monolithic voltage conversion operating at high
input supply voltages},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {464--467},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464625},
doi = {10.1109/ISCAS.2005.1464625},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/KursunSDFN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/IsmailKGTYD05,
author = {Yehea I. Ismail and
Muhammad M. Khellah and
Maged Ghoneima and
James W. Tschanz and
Yibin Ye and
Vivek De},
title = {Skewing adjacent line repeaters to reduce the delay and energy dissipation
of on-chip buses},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {592--595},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464657},
doi = {10.1109/ISCAS.2005.1464657},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/IsmailKGTYD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KeshavarziSTMBTZLHDBD05,
author = {Ali Keshavarzi and
Gerhard Schrom and
Stephen Tang and
Sean Ma and
Keith A. Bowman and
Sunit Tyagi and
Kevin Zhang and
Tom Linton and
Nagib Hakim and
Steven G. Duvall and
John Brews and
Vivek De},
editor = {Kaushik Roy and
Vivek Tiwari},
title = {Measurements and modeling of intrinsic fluctuations in {MOSFET} threshold
voltage},
booktitle = {Proceedings of the 2005 International Symposium on Low Power Electronics
and Design, 2005, San Diego, California, USA, August 8-10, 2005},
pages = {26--29},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1077603.1077611},
doi = {10.1145/1077603.1077611},
timestamp = {Tue, 30 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/KeshavarziSTMBTZLHDBD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/NarendraDBAC04,
author = {Siva G. Narendra and
Vivek De and
Shekhar Borkar and
Dimitri A. Antoniadis and
Anantha P. Chandrakasan},
title = {Full-chip subthreshold leakage power prediction and reduction techniques
for sub-0.18-{\(\mu\)}m {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {39},
number = {3},
pages = {501--510},
year = {2004},
url = {https://doi.org/10.1109/JSSC.2003.821776},
doi = {10.1109/JSSC.2003.821776},
timestamp = {Thu, 05 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/NarendraDBAC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HazuchaKWBTMSDN04,
author = {Peter Hazucha and
Tanay Karnik and
Steven Walstra and
Bradley A. Bloechel and
James W. Tschanz and
Jose Maiz and
Krishnamurthy Soumyanath and
Gregory E. Dermer and
Siva G. Narendra and
Vivek De and
Shekhar Borkar},
title = {Measurements and analysis of SER-tolerant latch in a 90-nm dual-V\({}_{\mbox{T}}\)
{CMOS} process},
journal = {{IEEE} J. Solid State Circuits},
volume = {39},
number = {9},
pages = {1536--1543},
year = {2004},
url = {https://doi.org/10.1109/JSSC.2004.831449},
doi = {10.1109/JSSC.2004.831449},
timestamp = {Wed, 27 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HazuchaKWBTMSDN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KursunNDF04,
author = {Volkan Kursun and
Siva G. Narendra and
Vivek K. De and
Eby G. Friedman},
title = {Low-voltage-swing monolithic dc-dc conversion},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {51-II},
number = {5},
pages = {241--248},
year = {2004},
url = {https://doi.org/10.1109/TCSII.2004.827557},
doi = {10.1109/TCSII.2004.827557},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KursunNDF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/VassighiKNSYLCSD04,
author = {Arman Vassighi and
Ali Keshavarzi and
Siva G. Narendra and
Gerhard Schrom and
Yibin Ye and
Seri Lee and
Greg Chrysler and
Manoj Sachdev and
Vivek De},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Design optimizations for microprocessors at low temperature},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {2--5},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996570},
doi = {10.1145/996566.996570},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/VassighiKNSYLCSD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/BorkarKD04,
author = {Shekhar Borkar and
Tanay Karnik and
Vivek De},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {Design and reliability challenges in nanometer technologies},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {75},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996588},
doi = {10.1145/996566.996588},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/BorkarKD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SchromHHKGNKD04,
author = {Gerhard Schrom and
Peter Hazucha and
Jae{-}Hong Hahn and
Volkan Kursun and
Donald S. Gardner and
Siva G. Narendra and
Tanay Karnik and
Vivek De},
editor = {Rajiv V. Joshi and
Kiyoung Choi and
Vivek Tiwari and
Kaushik Roy},
title = {Feasibility of monolithic and 3D-stacked {DC-DC} converters for microprocessors
in 90nm technology generation},
booktitle = {Proceedings of the 2004 International Symposium on Low Power Electronics
and Design, 2004, Newport Beach, California, USA, August 9-11, 2004},
pages = {263--268},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1013235.1013302},
doi = {10.1145/1013235.1013302},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/SchromHHKGNKD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KursunNDF04,
author = {Volkan Kursun and
Siva G. Narendra and
Vivek De and
Eby G. Friedman},
title = {High Input Voltage Step-Down {DC-DC} Converters for Integration in
a Low Voltage {CMOS} Process},
booktitle = {5th International Symposium on Quality of Electronic Design {(ISQED}
2004), 22-24 March 2004, San Jose, CA, {USA}},
pages = {517--521},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISQED.2004.1283725},
doi = {10.1109/ISQED.2004.1283725},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KursunNDF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/NarendraKBBD03,
author = {Siva G. Narendra and
Ali Keshavarzi and
Bradley A. Bloechel and
Shekhar Borkar and
Vivek De},
title = {Forward body bias for microprocessors in 130-nm technology generation
and beyond},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {5},
pages = {696--701},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.810054},
doi = {10.1109/JSSC.2003.810054},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/NarendraKBBD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TschanzNND03,
author = {James W. Tschanz and
Siva G. Narendra and
Raj Nair and
Vivek De},
title = {Effectiveness of adaptive supply voltage and body bias for reducing
impact of parameter variations in low power and high performance microprocessors},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {5},
pages = {826--829},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.810053},
doi = {10.1109/JSSC.2003.810053},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TschanzNND03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YeKSFD03,
author = {Yibin Ye and
Muhammad M. Khellah and
Dinesh Somasekhar and
Ali Farhang and
Vivek De},
title = {A 6-GHz 16-kB {L1} cache in a 100-nm dual-V\({}_{\mbox{T}}\) technology
using a bitline leakage reduction {(BLR)} technique},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {5},
pages = {839--842},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.810057},
doi = {10.1109/JSSC.2003.810057},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YeKSFD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TschanzNYBBD03,
author = {James W. Tschanz and
Siva G. Narendra and
Yibin Ye and
Bradley A. Bloechel and
Shekhar Borkar and
Vivek De},
title = {Dynamic sleep transistor and body bias for active leakage power control
of microprocessors},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {11},
pages = {1838--1845},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.818291},
doi = {10.1109/JSSC.2003.818291},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TschanzNYBBD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KursunNDF03,
author = {Volkan Kursun and
Siva G. Narendra and
Vivek De and
Eby G. Friedman},
title = {Analysis of buck converters for on-chip integration with a dual supply
voltage microprocessor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {3},
pages = {514--522},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812289},
doi = {10.1109/TVLSI.2003.812289},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KursunNDF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DeB03,
author = {Vivek De and
Luca Benini},
title = {Guest editorial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {753--754},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.818875},
doi = {10.1109/TVLSI.2003.818875},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DeB03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KeshavarziRHD03,
author = {Ali Keshavarzi and
Kaushik Roy and
Charles F. Hawkins and
Vivek De},
title = {Multiple-parameter {CMOS} {IC} testing with increased sensitivity
for I\({}_{\mbox{DDQ}}\)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {11},
number = {5},
pages = {863--870},
year = {2003},
url = {https://doi.org/10.1109/TVLSI.2003.812298},
doi = {10.1109/TVLSI.2003.812298},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KeshavarziRHD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/HazuchaKWBTMSDN03,
author = {Peter Hazucha and
Tanay Kamik and
Steven Walstra and
Bradley A. Bloechel and
James W. Tschanz and
Jose Maiz and
Krishnamurthy Soumyanath and
Greg Dermer and
Siva G. Narendra and
Vivek De and
Shekhar Borkar},
title = {Measurements and analysis of {SER} tolerant latch in a 90 nm dual-Vt
{CMOS} process},
booktitle = {Proceedings of the {IEEE} Custom Integrated Circuits Conference, {CICC}
2003, San Jose, CA, USA, September 21 - 24, 2003},
pages = {617--620},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CICC.2003.1249472},
doi = {10.1109/CICC.2003.1249472},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/HazuchaKWBTMSDN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/BorkarKNTKD03,
author = {Shekhar Borkar and
Tanay Karnik and
Siva G. Narendra and
James W. Tschanz and
Ali Keshavarzi and
Vivek De},
title = {Parameter variations and impact on circuits and microarchitecture},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {338--342},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.775920},
doi = {10.1145/775832.775920},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/BorkarKNTKD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZhangKVID03,
author = {Wei Zhang and
Mahmut T. Kandemir and
Narayanan Vijaykrishnan and
Mary Jane Irwin and
Vivek De},
title = {Compiler Support for Reducing Leakage Energy Consumption},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {11146--11147},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10085},
doi = {10.1109/DATE.2003.10085},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ZhangKVID03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/AlvandpourSKDBS03,
author = {Atila Alvandpour and
Dinesh Somasekhar and
Ram Krishnamurthy and
Vivek De and
Shekhar Borkar and
Christer Svensson},
editor = {Jos{\'{e}} E. Franca and
Rudolf Koch},
title = {Bitline leakage equalization for sub-100nm caches},
booktitle = {{ESSCIRC} 2003 - 29th European Solid-State Circuits Conference, Estoril,
Portugal, September 16-18, 2003},
pages = {401--404},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ESSCIRC.2003.1257157},
doi = {10.1109/ESSCIRC.2003.1257157},
timestamp = {Wed, 05 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/AlvandpourSKDBS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/TangND03,
author = {Stephen Tang and
Siva G. Narendra and
Vivek De},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {Temperature and process invariant MOS-based reference current generation
circuits for sub-1V operation},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {199--204},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871556},
doi = {10.1145/871506.871556},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/TangND03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/KursunNDF03,
author = {Volkan Kursun and
Siva G. Narendra and
Vivek De and
Eby G. Friedman},
title = {Monolithic {DC-DC} Converter Analysis And Mosfet Gate Voltage Optimization},
booktitle = {4th International Symposium on Quality of Electronic Design {(ISQED}
2003), 24-26 March 2003, San Jose, CA, {USA}},
pages = {279},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISQED.2003.1194746},
doi = {10.1109/ISQED.2003.1194746},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/KursunNDF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/KeshavarziTNDDRSH02,
author = {Ali Keshavarzi and
James W. Tschanz and
Siva G. Narendra and
Vivek De and
W. Robert Daasch and
Kaushik Roy and
Manoj Sachdev and
Charles F. Hawkins},
title = {Leakage and Process Variation Effects in Current Testing on Future
{CMOS} Circuits},
journal = {{IEEE} Des. Test Comput.},
volume = {19},
number = {5},
pages = {36--43},
year = {2002},
url = {https://doi.org/10.1109/MDT.2002.1033790},
doi = {10.1109/MDT.2002.1033790},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/KeshavarziTNDDRSH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TschanzKNNACD02,
author = {James W. Tschanz and
James T. Kao and
Siva G. Narendra and
Raj Nair and
Dimitri A. Antoniadis and
Anantha P. Chandrakasan and
Vivek De},
title = {Adaptive body bias for reducing impacts of die-to-die and within-die
parameter variations on microprocessor frequency and leakage},
journal = {{IEEE} J. Solid State Circuits},
volume = {37},
number = {11},
pages = {1396--1402},
year = {2002},
url = {https://doi.org/10.1109/JSSC.2002.803949},
doi = {10.1109/JSSC.2002.803949},
timestamp = {Mon, 04 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TschanzKNNACD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/VangalABSGEWPVT02,
author = {Sriram R. Vangal and
Mark A. Anders and
Nitin Borkar and
Erik Seligman and
Venkatesh Govindarajulu and
Vasantha Erraguntla and
Howard Wilson and
Amaresh Pangal and
Venkat Veeramachaneni and
James W. Tschanz and
Yibin Ye and
Dinesh Somasekhar and
Bradley A. Bloechel and
Gregory E. Dermer and
Ram K. Krishnamurthy and
Krishnamurthy Soumyanath and
Sanu Mathew and
Siva G. Narendra and
Mircea R. Stan and
Scott Thompson and
Vivek De and
Shekhar Borkar},
title = {5-GHz 32-bit integer execution core in 130-nm dual-V\({}_{\mbox{T}}\)
{CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {37},
number = {11},
pages = {1421--1432},
year = {2002},
url = {https://doi.org/10.1109/JSSC.2002.803944},
doi = {10.1109/JSSC.2002.803944},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/VangalABSGEWPVT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HamzaogluYKZNBSD02,
author = {Fatih Hamzaoglu and
Yibin Ye and
Ali Keshavarzi and
Kevin Zhang and
Siva G. Narendra and
Shekhar Borkar and
Mircea R. Stan and
Vivek De},
title = {Analysis of dual-V\({}_{\mbox{T}}\) {SRAM} cells with full-swing single-ended
bit line sensing for on-chip cache},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {2},
pages = {91--95},
year = {2002},
url = {https://doi.org/10.1109/92.994983},
doi = {10.1109/92.994983},
timestamp = {Fri, 26 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HamzaogluYKZNBSD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KrishnamurthyAD02,
author = {Ram K. Krishnamurthy and
Atila Alvandpour and
Vivek De and
Shekhar Borkar},
title = {High-performance and low-power challenges for sub-70 nm microprocessor
circuits},
booktitle = {Proceedings of the {IEEE} 2002 Custom Integrated Circuits Conference,
{CICC} 2002, Orlando, FL, USA, May 12-15, 2002},
pages = {125--128},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/CICC.2002.1012781},
doi = {10.1109/CICC.2002.1012781},
timestamp = {Tue, 04 Oct 2022 22:39:17 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KrishnamurthyAD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SeryBD02,
author = {George Sery and
Shekhar Borkar and
Vivek De},
title = {Life is {CMOS:} why chase the life after?},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {78--83},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.513941},
doi = {10.1145/513918.513941},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SeryBD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KarnikYTWBGDB02,
author = {Tanay Karnik and
Yibin Ye and
James W. Tschanz and
Liqiong Wei and
Steven M. Burns and
Venkatesh Govindarajulu and
Vivek De and
Shekhar Borkar},
title = {Total power optimization by simultaneous dual-Vt allocation and device
sizing in high performance microprocessors},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {486--491},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.514042},
doi = {10.1145/513918.514042},
timestamp = {Wed, 15 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/KarnikYTWBGDB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KarnikBD02,
author = {Tanay Karnik and
Shekhar Borkar and
Vivek De},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Sub-90nm technologies: challenges and opportunities for {CAD}},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {203--206},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774602},
doi = {10.1145/774572.774602},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KarnikBD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/NarendraDBAC02,
author = {Siva G. Narendra and
Vivek De and
Shekhar Borkar and
Dimitri A. Antoniadis and
Anantha P. Chandrakasan},
editor = {Vivek De and
Mary Jane Irwin and
Ingrid Verbauwhede and
Christian Piguet},
title = {Full-chip sub-threshold leakage power prediction model for sub-0.18
{\(\mathrm{\mu}\)}m {CMOS}},
booktitle = {Proceedings of the 2002 International Symposium on Low Power Electronics
and Design, 2002, Monterey, California, USA, August 12-14, 2002},
pages = {19--23},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/566408.566415},
doi = {10.1145/566408.566415},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/NarendraDBAC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/De02,
author = {Vivek De},
editor = {Sachin S. Sapatnekar and
Massoud Pedram},
title = {Leakage-tolerant design techniques for high performance processors},
booktitle = {Proceedings of 2002 International Symposium on Physical Design, {ISPD}
2002, Del Mar, CA, USA, April 7-10, 2002},
pages = {28--28},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505388.505396},
doi = {10.1145/505388.505396},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/De02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/WilsonND02,
author = {Ron Wilson and
Siva G. Narendra and
Vivek De},
title = {Evening Panel Discussion: Process Variation: Is It Too Much to Handle?},
booktitle = {3rd International Symposium on Quality of Electronic Design, {ISQED}
2002, San Jose, CA, USA, March 18-21, 2002},
pages = {213},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.ieeecomputersociety.org/10.1109/ISQED.2002.10015},
doi = {10.1109/ISQED.2002.10015},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/WilsonND02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SeguraDK02,
author = {Jaume Segura and
Vivek De and
Ali Keshavarzi},
title = {Challenges in Nanometric Technology Scaling: Trends and Projections},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {447--448},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.ieeecomputersociety.org/10.1109/VTS.2002.10014},
doi = {10.1109/VTS.2002.10014},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SeguraDK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2002,
editor = {Kanad Ghose and
Patrick H. Madden and
Vivek De and
Peter M. Kogge},
title = {Proceedings of the 12th {ACM} Great Lakes Symposium on {VLSI} 2002,
New York, NY, USA, April 18-19, 2002},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/505306},
doi = {10.1145/505306},
isbn = {1-58113-462-2},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/2002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/islped/2002,
editor = {Vivek De and
Mary Jane Irwin and
Ingrid Verbauwhede and
Christian Piguet},
title = {Proceedings of the 2002 International Symposium on Low Power Electronics
and Design, 2002, Monterey, California, USA, August 12-14, 2002},
publisher = {{ACM}},
year = {2002},
isbn = {1-58113-475-4},
timestamp = {Fri, 30 Apr 2004 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/2002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/TschanzNCBSD01,
author = {James W. Tschanz and
Siva G. Narendra and
Zhanping Chen and
Shekhar Borkar and
Manoj Sachdev and
Vivek De},
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Comparative delay and energy of single edge-triggered {\&} dual
edge-triggered pulsed flip-flops for high-performance microprocessors},
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
pages = {147--152},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/383082.383121},
doi = {10.1145/383082.383121},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/TschanzNCBSD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/NarendraDACB01,
author = {Siva G. Narendra and
Vivek De and
Dimitri A. Antoniadis and
Anantha P. Chandrakasan and
Shekhar Borkar},
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Scaling of stack effect and its application for leakage reduction},
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
pages = {195--200},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/383082.383132},
doi = {10.1145/383082.383132},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/NarendraDACB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KeshavarziMNBMGBD01,
author = {Ali Keshavarzi and
Sean Ma and
Siva G. Narendra and
Brad Bloechel and
K. Mistry and
Tahir Ghani and
Shekhar Borkar and
Vivek De},
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Effectiveness of reverse body bias for leakage control in scaled dual
Vt {CMOS} ICs},
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
pages = {207--212},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/383082.383135},
doi = {10.1145/383082.383135},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KeshavarziMNBMGBD01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/islped/2001,
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
publisher = {{ACM}},
year = {2001},
isbn = {1-58113-371-5},
timestamp = {Fri, 30 Apr 2004 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/2001.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SomasekharCRYD00,
author = {Dinesh Somasekhar and
Seung Hoon Choi and
Kaushik Roy and
Yibin Ye and
Vivek De},
editor = {Giovanni De Micheli},
title = {Dynamic noise analysis in precharge-evaluate circuits},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {243},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337406},
doi = {10.1145/337292.337406},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SomasekharCRYD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DeB00,
author = {Vivek De and
Shekhar Borkar},
editor = {Majid Sarrafzadeh and
Prithviraj Banerjee and
Kaushik Roy},
title = {Low power and high performance design challenges in future technologies},
booktitle = {Proceedings of the 10th {ACM} Great Lakes Symposium on {VLSI} 2000,
Chicago, Illinois, USA, March 2-4, 2000},
pages = {1--6},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/330855.330929},
doi = {10.1145/330855.330929},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/DeB00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/KeshavarziRHSSD00,
author = {Ali Keshavarzi and
Kaushik Roy and
Charles F. Hawkins and
Manoj Sachdev and
Krishnamurthy Soumyanath and
Vivek De},
title = {Multiple-parameter {CMOS} {IC} testing with increased sensitivity
for I{\_}DDQ},
booktitle = {Proceedings {IEEE} International Test Conference 2000, Atlantic City,
NJ, USA, October 2000},
pages = {1051--1059},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/TEST.2000.894318},
doi = {10.1109/TEST.2000.894318},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/KeshavarziRHSSD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/WeiRD00,
author = {Liqiong Wei and
Kaushik Roy and
Vivek De},
title = {Low Voltage Low Power {CMOS} Design Techniques for Deep Submicron
ICs},
booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
4-7 January 2000, Calcutta, India},
pages = {24--29},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICVD.2000.812579},
doi = {10.1109/ICVD.2000.812579},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/WeiRD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiCRJYD99,
author = {Liqiong Wei and
Zhanping Chen and
Kaushik Roy and
Mark C. Johnson and
Yibin Ye and
Vivek De},
title = {Design and optimization of dual-threshold circuits for low-voltage
low-power applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {7},
number = {1},
pages = {16--24},
year = {1999},
url = {https://doi.org/10.1109/92.748196},
doi = {10.1109/92.748196},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiCRJYD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WeiCRYD99,
author = {Liqiong Wei and
Zhanping Chen and
Kaushik Roy and
Yibin Ye and
Vivek De},
editor = {Mary Jane Irwin},
title = {Mixed-\emph{V\({}_{\mbox{th}}\)} {(MVT)} {CMOS} Circuit Design Methodology
for Low Power Applications},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {430--435},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309974},
doi = {10.1145/309847.309974},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WeiCRYD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/DeB99,
author = {Vivek De and
Shekhar Borkar},
editor = {Farid N. Najm and
Jason Cong and
David T. Blaauw},
title = {Technology and design challenges for low power and high performance},
booktitle = {Proceedings of the 1999 International Symposium on Low Power Electronics
and Design, 1999, San Diego, California, USA, August 16-17, 1999},
pages = {163--168},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/313817.313908},
doi = {10.1145/313817.313908},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/DeB99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KeshavarziNBHRD99,
author = {Ali Keshavarzi and
Siva G. Narendra and
Shekhar Borkar and
Charles F. Hawkins and
Kaushik Roy and
Vivek De},
editor = {Farid N. Najm and
Jason Cong and
David T. Blaauw},
title = {Technology scaling behavior of optimum reverse body bias for standby
leakage power reduction in {CMOS} IC's},
booktitle = {Proceedings of the 1999 International Symposium on Low Power Electronics
and Design, 1999, San Diego, California, USA, August 16-17, 1999},
pages = {252--254},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/313817.313937},
doi = {10.1145/313817.313937},
timestamp = {Mon, 28 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KeshavarziNBHRD99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PantDC98,
author = {P. Pant and
Vivek K. De and
A. Chatterjee},
title = {Simultaneous power supply, threshold voltage, and transistor size
optimization for low-power operation of {CMOS} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {6},
number = {4},
pages = {538--545},
year = {1998},
url = {https://doi.org/10.1109/92.736125},
doi = {10.1109/92.736125},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PantDC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WeiCJRD98,
author = {Liqiong Wei and
Zhanping Chen and
Mark Johnson and
Kaushik Roy and
Vivek De},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Design and Optimization of Low Voltage High Performance Dual Threshold
{CMOS} Circuits},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {489--494},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277179},
doi = {10.1145/277044.277179},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WeiCJRD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangDM97,
author = {Xinghai Tang and
Vivek De and
James D. Meindl},
title = {Intrinsic {MOSFET} parameter fluctuations due to random dopant placement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {5},
number = {4},
pages = {369--376},
year = {1997},
url = {https://doi.org/10.1109/92.645063},
doi = {10.1109/92.645063},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangDM97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PantDC97,
author = {Pankaj Pant and
Vivek De and
Abhijit Chatterjee},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {Device-Circuit Optimization for Minimal Energy and Power Consumption
in {CMOS} Random Logic Networks},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {403--408},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266181},
doi = {10.1145/266021.266181},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PantDC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/BhavnagarwalaDAM96,
author = {Azeez J. Bhavnagarwala and
Vivek De and
Blanca Austin and
James D. Meindl},
editor = {Mark Horowitz and
Jan M. Rabaey and
Brock Barton and
Massoud Pedram},
title = {Circuit techniques for low-power {CMOS} {GSI}},
booktitle = {Proceedings of the 1996 International Symposium on Low Power Electronics
and Design, 1996, Monterey, California, USA, August 12-14, 1996},
pages = {193--196},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/LPE.1996.547505},
doi = {10.1109/LPE.1996.547505},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/islped/BhavnagarwalaDAM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/TangDM96,
author = {Xinghai Tang and
Vivek De and
James D. Meindl},
editor = {Mark Horowitz and
Jan M. Rabaey and
Brock Barton and
Massoud Pedram},
title = {Effects of random {MOSFET} parameter fluctuations on total power consumption},
booktitle = {Proceedings of the 1996 International Symposium on Low Power Electronics
and Design, 1996, Monterey, California, USA, August 12-14, 1996},
pages = {233--236},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/LPE.1996.547514},
doi = {10.1109/LPE.1996.547514},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/TangDM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/DeM96,
author = {Vivek De and
James D. Meindl},
editor = {Mark Horowitz and
Jan M. Rabaey and
Brock Barton and
Massoud Pedram},
title = {A dynamic energy recycling logic family for ultra-low-power gigascale
integration {(GSI)}},
booktitle = {Proceedings of the 1996 International Symposium on Low Power Electronics
and Design, 1996, Monterey, California, USA, August 12-14, 1996},
pages = {371--375},
publisher = {{IEEE}},
year = {1996},
url = {https://doi.org/10.1109/LPE.1996.547541},
doi = {10.1109/LPE.1996.547541},
timestamp = {Fri, 30 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/DeM96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AgrawalDPM94,
author = {Bhavna Agrawal and
Vivek K. De and
Joseph M. Pimbley and
James D. Meindl},
title = {Short channel models and scaling limits of {SOI} and bulk MOSFETs},
journal = {{IEEE} J. Solid State Circuits},
volume = {29},
number = {2},
pages = {122--125},
year = {1994},
url = {https://doi.org/10.1109/4.272115},
doi = {10.1109/4.272115},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AgrawalDPM94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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